Semiconductor storage device and semiconductor integrated circuit

ABSTRACT

There is provided a semiconductor storage device capable of high integration. On a top surface of a semiconductor substrate, a plurality of device isolation regions ( 16 ) each extending and meandering in a lateral direction are formed so as to be arrayed with respect to a longitudinal direction, by which active regions are defined between neighboring ones of the device isolation regions ( 16 ), respectively. Dopant diffusion regions (source or drain) are formed at individual turnover portions (corresponding to contacts ( 14 ), ( 15 )), respectively, of the meanders within the active regions. A plurality of word lines ( 11 ) extending straight in the longitudinal direction run on the channel regions within the active regions via a film having memory function, respectively. A first bit line ( 12 ) extending straight in the lateral direction runs on the dopant diffusion region (corresponding to contact ( 14 )) provided at a crest-side turnover portion. A second bit line ( 15 ) extending straight in the lateral direction runs on the dopant diffusion region (corresponding to contact ( 15 )) provided at a trough-side turnover portion.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor storage deviceformed of field effect transistor (FET) type memory cells equipped withmemory-functional film, and to a semiconductor integrated circuitincluding the semiconductor storage device.

BACKGROUND ART

[0002] Flash memory has been widely used as a memory using thresholdchanges of MOS (Metal Oxide Semiconductor) FETs due to the charge amountof the floating gate that is the memory-functional film. Among1-transistor type memories of the flash memory are NOR type, DINOR type,NAND type, AND type, and the like. Among them, the AND type has acharacteristic that it can be made smaller in cell area and stillequivalent in read speed, compared with the NOR type. Further, the ANDtype is enabled to perform erase operations on the word line basis, thushaving a characteristic that it is smaller in erase unit than the NANDtype.

[0003] However, in the above-described conventional AND type memory, thecell area is about 8F² (where F is a minimum machining pitch), largerthan 6F² of the NAND type memory, which has been an obstacle to higherintegration as a problem.

[0004] A detailed explanation is given below. FIG. 32 shows a planarpattern layout in the conventional AND type memory cell array. Referringto FIG. 32, in the conventional AND type cell array, a plurality ofdevice isolation regions 1 for partitioning the semiconductor substrateare formed so as to extend straight in one direction (lateral directionin FIG. 32). The pitch of the device isolation regions 1 along thelongitudinal direction is set to 4F. Between one pair of deviceisolation regions 1, 1, a source line 2 and a bit line 3 each composedof a dopant diffusion layer in the semiconductor substrate are formed soas to extend straight in the lateral direction and to be spaced fromeach other by a distance of 1F. On the other hand, in the verticaldirection (longitudinal direction in FIG. 32) against the lateraldirection, a plurality of word lines 4 composed of polycrystallinesilicon are formed so as to extend straight at a pitch of 2F in thelateral direction. Then, a region interposed between the source line 2and the bit line 3 and covered with a word line 4 becomes a channelregion 5. One memory cell is a region represented by a longitudinally 4Fand laterally 2F sized rectangular shape 6 depicted by two-dot chainline in FIG. 32, the area thereof being 8F² (=4F×2F) larger than that ofthe NAND type memory, 6F².

[0005] As shown above, the AND type memory, although having suchcharacteristics as the read speed equivalent to that of the NOR type andthe capability of word-line basis erase operation, which is smaller thanin the NAND type, yet has the problems of larger area and incapabilityof higher integration as compared with the NAND type.

DISCLOSURE OF THE INVENTION

[0006] (Technical Issues to be Solved by the Invention)

[0007] Accordingly, an object of the present invention is to provide asemiconductor storage device smaller in one-memory cell area and higherin feasible integration than those of the NAND type, as well as toprovide a semiconductor integrated circuit having the semiconductorstorage device.

[0008] In order to achieve the above object, in a first aspect of thepresent invention, there is provided a semiconductor storage devicecharacterized in that:

[0009] on a top surface of a semiconductor substrate, device isolationregions each extending and meandering in one direction are formed so asto be arrayed with respect to a direction vertical to the one direction,and active regions each extending in the one direction are definedbetween neighboring ones of the device isolation regions, respectively;

[0010] dopant diffusion regions each serving as a source region or drainregion are formed at individual turnover portions, respectively, ofmeanders within the active regions, and channel regions are definedbetween neighboring ones of the dopant diffusion regions withinidentical active regions, respectively;

[0011] on the semiconductor substrate, word lines extending inintersection with the one direction are provided so as to run on thechannel regions provided within the active regions; and

[0012] on the semiconductor substrate, a plurality of bit linesextending in the one direction are provided so as to run on the dopantdiffusion regions, and are also connected to the dopant diffusionregions present thereunder via contact holes, respectively.

[0013] In this constitution, not that the dopant diffusion layer in thesemiconductor substrate is taken as bit lines as has been in the priorart, but that bit lines are formed on the semiconductor substrate andconnected to the dopant diffusion regions (source region or drainregion) present thereunder via contact holes. Also, the active regionsare meandering, and the dopant diffusion regions are formed atindividual turnover portions of the meanders. Therefore, it becomesimplementable that a plurality of bit lines or a bit line and a plateelectrode are provided on an identical active region and moreover eachconnected to the source region or drain region. Further, the dopantdiffusion regions formed at individual turnover portions of the meanderswithin the active regions, respectively, are each paired with a dopantdiffusion region neighboring within the same active region via thechannel region, thus serving as a source region/drain region of thefield effect transistor. That is, the dopant diffusion regions areshared each by two field effect transistors. Therefore, the device areacan be reduced.

[0014] From the above reasons, according to the semiconductor storagedevice of this embodiment, the area of one cell can be made smaller thanthat of the conventional AND type memory cell array. Therefore, higherintegration becomes implementable, the product yield improves, and themanufacturing cost can be reduced.

[0015] In an embodiment, the plurality of bit lines comprise a first bitline provided so as to run on the dopant diffusion region provided at aone-side turnover portion of the meander within an identical activeregion, and a second bit line provided so as to run on the dopantdiffusion region provided at the other-side turnover portion of themeander within the identical active region.

[0016] In this embodiment, within the identical active region, the firstbit line is provided on the dopant. diffusion region provided at aone-side turnover portion of the meander, while the second bit line isprovided on the dopant diffusion region provided at the other-sideturnover portion of the meander, where the individual bit lines and thedopant diffusion regions present thereunder are connected to each othervia contact holes, respectively. Therefore, each dopant region connectedto the first bit line can be assigned to serve as one of the sourceregion and the drain region, while each dopant region connected to thesecond bit line can be assigned to serve as the other of the sourceregion and the drain region. Further, in the planar pattern layout,there is no need for any margin that isolates the first bit line and thesecond bit line from each other, and the first bit lines (second bitlines) can be arrayed at a pitch of 2F in a direction intersecting withthe one direction. Thus, the area of one cell can be further reduced,for example, to 4F².

[0017] Furthermore, the source region and the drain region can be givenvoltages that are independent from bit line to bit line. Therefore, forexample, with the use of a silicon nitride film as the charge-trappingfilm, it becomes implementable to store 2-bit information by onetransistor when the source region and the drain region are functionallyreplaced with each other.

[0018] In one embodiment, the first bit line and the second bit line areformed of different interconnect layers electrically isolated by aninterlayer insulator, respectively.

[0019] In this embodiment, the first bit line and the second bit lineare formed of different interconnect layers that differ in height fromthe semiconductor substrate from each other. Therefore, even if there isno margin for isolating the first bit line and the second bit line fromeach other on the planar pattern layout, the isolation between the firstbit line and the second bit line can be easily achieved.

[0020] In one embodiment, the plurality of bit lines are alternatelyconnected to the dopant diffusion regions present thereunder via contactholes, respectively; and

[0021] plate electrodes are connected to dopant diffusion regions towhich the plurality of bit lines are not connected.

[0022] In this embodiment, one of the source region and the drain regionis connected to the bit line, and the other one of the source region andthe drain region is connected to the plate electrode. That is, only onebit line is present on the identical active region.

[0023] Therefore, as compared to the case where a plurality of bit linesare provided on the identical active region, the semiconductor storagedevice is simpler in interconnect structure, thus being easier tomanufacture. Further, since the plate electrode has only to be given aconstant voltage at all times as an example, the circuit for driving thememory can be simplified so that higher integration of the semiconductorstorage device as well as its cost reduction are achieved.

[0024] In one embodiment, a film having memory function is presentbetween gate electrode forming part of the word line and channel region.

[0025] In this embodiment, by applying a potential difference to betweenthe gate electrode and the channel region or the source/drain region,rewrite operation can be easily performed on the film having memoryfunction. The film having memory function also has a function as a gateinsulator, so that stored information can be easily detected as changesin the threshold of the field effect transistor.

[0026] In one embodiment, a film having memory function is present on aside wall of the gate electrode forming part of the word line.

[0027] In this embodiment, since a film having memory function isprovided on the side wall of the gate electrode, the gate insulator doesnot need to have the memory effect, thus being easily formed into athinner film. As a result, the short-channel effect can be easilysuppressed. Further, the film having memory function is separatedeffectively, so that 2-bit operation can be easily implemented.Therefore, micro-finer implementation and cost reduction of thesemiconductor storage device is achieved.

[0028] Also, in a second aspect of the present invention, there isprovided a semiconductor storage device characterized in that:

[0029] on a top surface of a semiconductor substrate, device isolationregions each extending in one direction are formed so as to be arrayedwith respect to a direction vertical to the one direction, and activeregions each extending in the one direction are defined betweenneighboring ones of the device isolation regions, respectively;

[0030] dopant diffusion regions each serving as a source region or drainregion are formed within the active regions, and channel regions aredefined between neighboring ones of the dopant diffusion regions withinidentical active regions, respectively;

[0031] on the semiconductor substrate, a plurality of word linesextending in intersection with the one direction are provided so as torun on the channel regions provided within the active regions;

[0032] on the semiconductor substrate, a plurality of bit linesextending in the one direction are provided so as to run on the dopantdiffusion regions, and are also connected to the dopant diffusionregions present thereunder via contact holes, respectively; and

[0033] the semiconductor substrate has a well region on its top surfaceside, the well region being electrically partitioned by the deviceisolation regions to form third bit lines.

[0034] In this constitution, not that the dopant diffusion layer in thesemiconductor substrate is taken as bit lines as has been in the priorart, but that bit lines are formed on the semiconductor substrate andconnected to the dopant diffusion regions (source region or drainregion) present thereunder via contact holes. Therefore, it becomesimplementable that a plurality of bit lines or a bit line and a plateelectrode are provided on an identical active region and moreover eachconnected to the source region or drain region. The well regionelectrically partitioned by the device isolation regions serves as athird bit line. During the operation of the semiconductor storagedevice, by selecting specific ones out of a plurality of third bitlines, applied voltage is variable on the third-bit-line basis, i.e., onthe well region basis. Therefore, by applying proper voltages to the bitlines and the third bit lines, rewrite operation on the 1-bit basisbecomes implementable. Thus, a semiconductor storage device capable ofrandom access is offered.

[0035] In one embodiment, the plurality of bit lines comprise a firstbit line connected to one of the source region or the drain region, anda second bit line connected to the other one of the source region or thedrain region.

[0036] In this embodiment, the source region and the drain region can begiven voltages that are independent from bit line to bit line.Therefore, for example, with the use of a silicon nitride film as thecharge-trapping film, it becomes implementable to store 2-bitinformation by one transistor when the source region and the drainregion are functionally replaced with each other.

[0037] Also, in a third aspect of the present invention, there isprovided a semiconductor storage device characterized in that:

[0038] on a top surface of a semiconductor substrate, device isolationregions each extending and meandering in one direction are formed so asto be arrayed with respect to a direction vertical to the one direction,and active regions each extending in the one direction are definedbetween neighboring ones of the device isolation regions, respectively;

[0039] dopant diffusion regions each serving as a source region or drainregion are formed at individual turnover portions, respectively, ofmeanders within the active regions, and channel regions are definedbetween neighboring ones of the dopant diffusion regions withinidentical active regions, respectively;

[0040] on the semiconductor substrate, a plurality of word linesextending in intersection with the one direction are provided so as torun on the channel regions provided within the active regions;

[0041] on the semiconductor substrate, a plurality of bit linesextending in the one direction are provided so as to run on the dopantdiffusion regions, and are also connected to the dopant diffusionregions present thereunder via contact holes, respectively; and

[0042] the semiconductor substrate has a well region on its top surfaceside, the well region being electrically partitioned by the deviceisolation regions to form third bit lines.

[0043] With this constitution, also, working effects similar to those ofthe semiconductor storage device of the second aspect are produced.Furthermore, the active regions are meandering, and the dopant diffusionregions are formed at individual turnover portions of the meanders.Therefore, it becomes implementable that a plurality of bit lines or abit line and a plate electrode are provided on an identical activeregion and moreover each connected to the source region or drain region.Further, the dopant diffusion regions formed at individual turnoverportions of the meanders within the active regions, respectively, areeach paired with a dopant diffusion region neighboring within the sameactive region via the channel region, thus serving as a sourceregion/drain region of the field effect transistor. That is, the dopantdiffusion regions are shared each by two field effect transistors.Therefore, the device area can be reduced.

[0044] Consequently, according to the semiconductor storage device ofthe third aspect, high integration and random access are implementable.

[0045] In one embodiment, the plurality of bit lines comprise a firstbit line provided so as to run on the dopant diffusion region providedat a one-side turnover portion of the meander within an identical activeregion, and a second bit line provided so as to run on the dopantdiffusion region provided at the other-side turnover portion of themeander within the identical active region.

[0046] In this embodiment, within the identical active region, the firstbit line is provided on the dopant diffusion region provided at aone-side turnover portion of the meander, while the second bit line isprovided on the dopant diffusion region provided at the other-sideturnover portion of the meander, where the individual bit lines and thedopant diffusion regions present thereunder are connected to each othervia contact holes, respectively. Therefore, each dopant region connectedto the first bit line can be assigned to serve as one of the sourceregion and the drain region, while each dopant region connected to thesecond bit line can be assigned to serve as the other of the sourceregion and the drain region. Further, in the planar pattern layout,there is no need for any margin that isolates the first bit line and thesecond bit line from each other, and the first bit lines (second bitlines) can be arrayed at a pitch of 2F in a direction intersecting withthe one direction. Thus, the area of one cell can be further reduced,for example, to 4F².

[0047] Furthermore, the source region and the drain region can be givenvoltages that are independent from bit line to bit line. Therefore, forexample, with the use of a silicon nitride film as the charge-trappingfilm, it becomes implementable to store 2-bit information by onetransistor when the source region and the drain region are functionallyreplaced with each other.

[0048] In one embodiment, the first bit line and the second bit line areformed of different interconnect layers electrically isolated by aninterlayer insulator, respectively.

[0049] In this embodiment, the first bit line and the second bit lineare formed of different interconnect layers that differ in height fromthe semiconductor substrate from each other. Therefore, even if there isno margin for isolating the first bit line and the second bit line fromeach other on the planar pattern layout, the isolation between the firstbit line and the second bit line can be easily achieved.

[0050] In one embodiment, the plurality of bit lines are alternatelyconnected to the dopant diffusion regions present thereunder via contactholes, respectively; and

[0051] plate electrodes are connected to dopant diffusion regions towhich the plurality of bit lines are not connected.

[0052] In this embodiment, one of the source region and the drain regionis connected to the bit line, and the other one of the source region andthe drain region is connected to the plate electrode. That is, only onebit line is present on the identical active region.

[0053] Therefore, as compared to the case where a plurality of bit linesare provided on the identical active region, the semiconductor storagedevice is simpler in interconnect structure, thus being easier tomanufacture. Further, since the plate electrode has only to be given aconstant voltage at all times as an example, the circuit for driving thememory can be simplified so that higher integration of the semiconductorstorage device as well as its cost reduction are achieved.

[0054] In one embodiment, a film having memory function is presentbetween gate electrode forming part of the word line and channel region.

[0055] In this embodiment, by applying a potential difference to betweenthe gate electrode and the channel region or the source/drain region,rewrite operation can be easily performed on the film having memoryfunction. The film having memory function also has a function as a gateinsulator, so that stored information can be easily detected as changesin the threshold of the field effect transistor.

[0056] In one embodiment, a film having memory function is present on aside wall of the gate electrode forming part of the word line.

[0057] In this embodiment, since a film having memory function isprovided on the side wall of the gate electrode, the gate insulator doesnot need to have the memory effect, thus being easily formed into athinner film. As a result, the short-channel effect can be easilysuppressed. Further, the film having memory function is separatedeffectively, so that 2-bit operation can be easily implemented.Therefore, micro-finer implementation and cost reduction of thesemiconductor storage device is achieved.

[0058] In one embodiment, the film having memory function is adielectric film containing fine particles formed of a semiconductor orconductor in a dot form.

[0059] In this specification, the term “fine particles” refers toparticles having a size of the nanometer (nm) order.

[0060] In this embodiment, since the film having memory function is adielectric film containing fine particles formed of a semiconductor orconductor in a dot form, the storage leakage is reduced. Therefore,device reliability can be improved. Further, since electric charges areaccumulated within the dot-form fine particles, the semiconductorstorage device is suited to the mode of 2-bit by 1-transistor.

[0061] In one embodiment, the film having memory function is amultilayered film of a silicon nitride film and a silicon oxide film.

[0062] In this embodiment, since the film having memory function is amultilayered film of a silicon nitride film and a silicon oxide film,the film has a function of trapping electric charges. Therefore, theleakage of storage charges is reduced. Thus, device reliability can beimproved. Further, since the electric charges are accumulated locallywithin the silicon nitride film, the semiconductor storage device issuited to the mode of 2-bit by 1-transistor.

[0063] In one embodiment, the film having memory function is sostructured that a silicon nitride film is sandwiched by silicon oxidefilms.

[0064] In this embodiment, since the film having memory function is sostructured that a silicon nitride film is sandwiched by silicon oxidefilms, injected storage charges can effectively be trapped. Therefore,the memory-film performance can be further improved.

[0065] In one embodiment, the film having memory function is sostructured that a silicon film is sandwiched by silicon oxide films.

[0066] In this embodiment, since the film having memory function is sostructured that a silicon film is sandwiched by silicon oxide films,there is an advantage that manufacturing process similar to that forflash memory can be used. Thus, a memory cell of small area can beimplemented by a manufacturing process of established reliability.

[0067] In one embodiment, the silicon film is formed of polysilicon.

[0068] In this embodiment, since the silicon film is formed ofpolysilicon, the silicon film can be formed by ordinary LPCVD equipment.Thus, a memory cell of small area can be implemented relatively simply.

[0069] In one embodiment, part of the word line present on the channelregion forms a gate electrode.

[0070] In this embodiment, since part of the word line present on thechannel region forms a gate electrode, there is no need for using anycontact or upper interconnection to connect the gate electrode and theword line to each other. Therefore, the structure of the memory cell issimplified, so that the manufacturing process can be reduced. Thus, themanufacturing cost can be lowered.

[0071] In one embodiment, in a write operation or an erase operation,

[0072] in a selected memory cell, if an absolute value V of a potentialdifference between the word line and the bit line, or an absolute valueV of a potential difference between the word line and the first bitline, or an absolute value V of a potential difference between the wordline and the second bit line, or an absolute value V of a potentialdifference between the word line and the third bit line, is V=V_(DD),

[0073] then a relationship that V_(DD)/3≦V<V_(DD)/2 is satisfied withrespect to a memory cell connected to only either one of a selected wordline and a selected bit line.

[0074] The ratio of the voltage applied to the selected memory cell tothe maximum value of voltages applied to the non-selected memory cellsbecomes a large one. Therefore, a memory of large operational margin isimplemented.

[0075] Furthermore, in a fourth aspect of the present invention, thereis provided a semiconductor integrated circuit in which thesemiconductor storage device according to any one of the first to thirdaspects of the present invention and a logic circuit are compositelymounted.

[0076] With this constitution, it becomes implementable, for example, towrite a large-scale program temporarily, hold the program even after theturn-off of power, and execute the program also after the reentry ofpower. Thus, functional improvement becomes achievable.

BRIEF DESCRIPTION OF THE DRAWINGS

[0077]FIG. 1 is a view showing the planar pattern of a first embodimentof a semiconductor storage device of the invention;

[0078]FIG. 2 is a sectional view taken in the direction of arrows alongthe line A-A′ of FIG. 1;

[0079]FIG. 3 is a sectional view taken in the direction of arrows B-B′of FIG. 1;

[0080]FIG. 4 is a sectional view taken in the direction of arrows C-C′of FIG. 1;

[0081]FIG. 5 is a circuit diagram of the semiconductor storage device ofthe first embodiment;

[0082]FIG. 6 is a sectional view of a semiconductor storage device of asecond embodiment;

[0083]FIG. 7 is a circuit diagram of the semiconductor storage device ofthe second embodiment;

[0084]FIG. 8 is a schematic sectional view of a semiconductor storagedevice of a second-a embodiment;

[0085]FIG. 9 is a schematic sectional view of a semiconductor storagedevice of a second-b embodiment;

[0086]FIG. 10 is a schematic sectional view of a semiconductor storagedevice of a fourth embodiment;

[0087]FIG. 11 is a schematic view showing a planar pattern of asemiconductor storage device of a fifth embodiment;

[0088]FIG. 12 is a sectional view taken in the direction of arrows G-G′of FIG. 11;

[0089]FIG. 13 is a sectional view taken in the direction of arrows H-H′of FIG. 11;

[0090]FIG. 14 is a schematic view showing a planar pattern of amodification of the fifth embodiment;

[0091]FIG. 15 is a sectional view taken in the direction of arrows I-I′of FIG. 14;

[0092]FIG. 16 is a sectional view taken in the direction of arrows J-J′of FIG. 14;

[0093]FIG. 17 is a circuit diagram of the semiconductor storage deviceof the fifth embodiment;

[0094]FIG. 18 is a sectional view of a semiconductor storage device of asixth embodiment;

[0095]FIG. 19 is a sectional view along a direction different from thatof FIG. 18;

[0096]FIG. 20 is a sectional view of a modification of the sixthembodiment;

[0097]FIG. 21 is a sectional view along a direction different from thatof FIG. 20;

[0098]FIG. 22 is a circuit diagram of the semiconductor storage deviceof the sixth embodiment;

[0099]FIG. 23 is a sectional view of a memory cell in anothermodification of the sixth embodiment;

[0100]FIG. 24 is a sectional view of a memory cell in a semiconductorstorage device of a seventh embodiment;

[0101]FIG. 25 is a sectional view of a memory cell in a semiconductorstorage device of an eighth embodiment;

[0102]FIG. 26 is a sectional view of a memory cell in a semiconductorstorage device of a ninth embodiment;

[0103]FIG. 27 is a sectional view of a memory cell in a semiconductorstorage device of a tenth embodiment;

[0104]FIG. 28 is a chart showing the relationship between capacity C ofthe memory-functional film and applied voltage Vg (+3V→−3V→+3V) in FIG.27;

[0105]FIG. 29 is a chart showing the relationship between capacity C andapplied voltage Vg (+1V→−1V→+1V) different from that of FIG. 27;

[0106]FIG. 30 is a sectional view of a memory cell in a semiconductorstorage device of a twelfth embodiment;

[0107]FIG. 31 is a sectional view of a memory cell in a semiconductorstorage device of a thirteenth embodiment; and

[0108]FIG. 32 is a view showing a planar pattern in a conventional ANDtype memory cell array.

BEST MODE FOR CARRYING OUT THE INVENTION

[0109] Hereinbelow, the present invention is described in detail by wayof embodiments thereof illustrated in the accompanying drawings. Thesemiconductor substrate to which the present invention can be applied,although not particularly limited, is preferably given by a siliconsubstrate. Also, the semiconductor substrate may have P or N conductivetype. It is noted that each of the following embodiments show a casewhere a silicon substrate is used. Even with an N-type or P-type siliconsubstrate used, similar semiconductor storage devices of similarfunctions can be formed by similar processes. Furthermore, although eachof the following embodiments is described on a case where an N-typedevice is used as a memory, a P-type device may be used as a memorywithout any problem. In that case, the conductive type of injectiondopants may appropriately be inverted in all cases.

[0110] (First Embodiment)

[0111] This embodiment is explained as follows with reference to FIGS. 1to 5.

[0112] FIGS. 1 to 4 are schematic views of a memory cell array which isa semiconductor storage device that forms this embodiment. FIG. 1 is aschematic view thereof. FIG. 2 is a sectional view as taken along thecut-plane line A-A′ of FIG. 1, FIG. 3 is a sectional view as taken alongthe cut-plane line B-B′ of FIG. 1, and FIG. 4 is a sectional view astaken along the cut-plane line C-C′ of FIG. 1. FIG. 5 is a circuitdiagram of a memory cell array which is the semiconductor storage devicethat forms the first embodiment of the invention.

[0113] First, constitution of the semiconductor storage device of thisembodiment is explained with reference to FIGS. 1 to 4. As can be seenfrom FIGS. 2 to 4, a P-type well region 18 is formed in a siliconsubstrate 17. Further, a plurality of device isolation regions 16 areformed so as to meander and extend in the lateral direction of FIG. 1(respective meandering band regions are hatched in FIG. 1). Thelongitudinal pitch of the device isolation regions 16 is set to 2F(where F is the minimum machining pitch). As a result of this, siliconactive regions each meandering and extending laterally are left betweenneighboring device isolation regions 16 in an upper portion of theP-type well region 18. The device isolation regions 16 are set to such adepth that next-described N⁺ diffusion layers 19 are electricallyisolated from each other but that the P-type well region 18 is notelectrically isolated.

[0114] As can be understood by generalizing FIGS. 1 to 4, N⁺ diffusionlayers 19 are formed at turnover portions, respectively, of the meanderswithin the silicon active region (portions corresponding to contacts 14,15). Each N⁺ diffusion layer 19 serves as a source region or drainregion depending on selection by bit lines during the use of thismemory. In this connection, regions between neighboring N⁺ diffusionlayers 19 within identical active regions serve as channel regions,respectively.

[0115] A plurality of word lines 11 composed of polysilicon are formedso as to extend straight along a direction vertical to the direction inwhich the device isolation regions 16 extend (i.e., along thelongitudinal direction in FIG. 1). The pitch of the word lines 11 alongthe lateral direction is set to 2F. A silicon active region (upperportion of the P-type well region 18) covered with a word line 11 is achannel region. The channel region and the word line 11 are isolatedfrom each other by a multilayered film composed of a tunnel oxide film23, a floating gate 21 and an oxide film 24. On this channel region, theword line 11 serves as a control gate.

[0116] A plurality of first bit lines 12 formed of a first-layer metalare formed so as to extend straight in a vertical direction (lateraldirection in FIG. 1) with respect to the word lines 11. The first bitlines 12, whose longitudinal pitch is set to 2F, are provided so as torun on the N⁺ diffusion layers 19 provided at one-side (crest side inFIG. 1) turnover portions of the meanders within identical siliconactive regions. These first bit lines 12 and the N⁺ diffusion layers 19located just thereunder are disposed at a pitch of 4F in the lateraldirection and connected by first bit line contacts 14. Also, a pluralityof second bit lines 13 formed of a second-layer metal are formed in thesame direction as the first bit lines 12 and at positions forming gapsof the first bit lines so as to extend straight parallel to the firstbit lines. The second bit lines 13, whose longitudinal pitch is set to2F, are provided so as to pass on the N⁺ diffusion layers 19 provided atthe other-side (trough side in FIG. 1) turnover portions of the meanderswithin identical silicon active regions. These second bit lines 13 andthe N⁺ diffusion layers 19 located just thereunder are disposed at apitch of 4F in the lateral direction and connected by second bit linecontacts 15. The first and second bit lines 12, 13 are isolated fromeach other by an interlayer insulator 20, and connected to the N⁺diffusion layers 19 by the contacts 14, 15 at necessary places asdescribed above, respectively.

[0117] According to this constitution, one memory cell is represented bya parallelogram 22 depicted by two-dot chain line in FIG. 1, its areabeing 4F².

[0118] The reason why the area of the memory cell of this embodiment canbe reduced than in the prior art is as follows. First, not that thedopant diffusion layer in the semiconductor substrate is taken as bitlines as has been in the prior art, but that the first and second bitlines 12, 13 are formed on the silicon substrate. Therefore, the firstbit lines 12 and the second bit lines 13 can be formed by usingdifferent interconnect layers isolated from each other by an interlayerinsulator 20. As a result, in the planar pattern layout, there is noneed for any margin that isolates the first and second bit lines 12, 13from each other. The direct reason why such a layout has been enabled isthat the shape of the active regions (regions other than the deviceisolation regions 16) is a wavy one having a period of 4F with respectto the lateral direction. Secondly, an N⁺ diffusion layer 19 formed ateach turnover portion of the meanders within the individual activeregions serve as a source region or drain region of a field effecttransistor as it is paired with another N⁺ diffusion layer 19neighboring thereto via the channel region within the identical activeregion. That is, each N⁺ diffusion layer 19 is shared by two fieldeffect transistors. Thus, the device area can be further reduced.

[0119] Next, circuit construction of the semiconductor storage device ofthis embodiment is explained with reference to FIG. 5. This memory cellarray is of the so-called AND type array. That is, one first bit lineand one second bit line are one paired with each other, and n (n:natural number) memory cells are connected in parallel between these bitlines. In FIG. 5, for example, a first bit line of a first bit line pairis expressed as Ba1 and a second bit line of the first bit line pair isexpressed as Bb1. Also, for example, an n-th memory cell connected tothe first bit line pair is expressed as M1n. A selector transistor isprovided for each bit line. In FIG. 5, for example, a first-bit-lineselector transistor for the first bit line pair is expressed as STBa1.Also, n word lines run vertical to the bit lines, respectively, toconnect memory-cell gates to one another. In FIG. 5, the word lines areexpressed as W1 to Wn.

[0120] Next, an operation example of the semiconductor storage device ofthis embodiment is explained with reference to FIG. 5. As an example, itis assumed that a state of low threshold of the memory cell is a writestate, while a state of high threshold of the memory cell is an erasestate. Further as an example, it is assumed that the drain region isconnected to the first bit line while the source region is connected tothe second bit line. Referring to FIG. 5, for a write operation into amemory cell M12, a negative voltage (e.g., −8 V) is applied to the wordline W2, a positive voltage (e.g., 6 V) is applied to the first bit lineBa1, and further the selector transistor STBa1 is turned on. In thiscase, the selector transistor STBa1 is turned off (where the sourceregion is open), and the P-type well region is set to ground voltage. Bydoing so, a high voltage is applied to between the control gate of thememory cell M12 and the drain region, so that electrons are pulled outfrom the floating gate to the drain region by FN (Fowler-Nordheim)tunneling, by which the write operation is accomplished.

[0121] On the other hand, an erase operation is performed collectivelyfor all memory cells on a selected word line. Referring to FIG. 5, forerasing the memory cells M12 and M22, a positive voltage (e.g., 10 V) isapplied to the word line W2, a negative voltage (e.g., −8 V) is appliedto the second bit lines Bb1 and Bb2, and the selector transistors STBb1and STBb2 are turned on. In this case, the selector transistors STBa1and STBa2 are turned off (where the drain region is open), and −8 V isapplied to the common P-type well region. By doing so, a high voltage isapplied to between the control gates of the memory cells M12 and M22 andthe P-type well region, so that electrons are injected from the P-typewell region to the floating gate by FN tunneling, by which the eraseoperation is accomplished.

[0122] In FIG. 5, for a read operation of data of the memory cell M12, apositive voltage (e.g., 3 V) is applied to the word line W2, a positivevoltage (e.g., 1 V) is applied to the first bit line Ba1, and furtherthe selector transistor STBa1 is turned on. In this case, the second bitline Bb1 is set to ground voltage, the selector transistor STBb1 isturned on, and the source of the memory cell M12 is set to groundvoltage. In addition, the P-type well region is set to ground voltage.By doing so, the data of the memory cell M12 can be read out.

[0123] It is noted that the set voltages of individual nodes for write,erase and read operations are not limited the above voltages.

[0124] Furthermore, it is also possible that the memory, which is thesemiconductor storage device of this embodiment, and the logic circuitare compositely mounted on one integrated circuit. It is furtherpossible that other memories (DRAM, SRAM, etc.) are also mounted inaddition to the memory, which is the semiconductor storage device ofthis embodiment, and the logic circuit. In that case, larger areas canbe allocated for the logic circuit or other memories in proportion tothe decrease of the area occupied by the memory that is thesemiconductor storage device of this embodiment, making it possible toachieve functional improvement. Otherwise, larger storage capacity canbe allocated for the memory that is the semiconductor storage device ofthis embodiment. In that case, for example, it becomes implementable towrite a large-scale program temporarily, hold the program even after theturn-off of power, and execute the program also after the reentry ofpower, and moreover to replace the program with another program.

[0125] Next, the procedure for fabricating the semiconductor storagedevice of this embodiment is explained. First, dielectric deviceisolation regions 16 are formed in the silicon substrate 17, andsubsequently a P-type well region 18 is formed. Thereafter, tunnel oxidefilm 23 is formed by thermal oxidation, and a polysilicon film is formedby CVD (Chemical Vapor Deposition) process. This polysilicon film ispatterned by photolithography and etching, by which a floating gate 21is formed. After that, an oxide film and a polysilicon film are formedin this order each by CVD process. These polysilicon film, oxide filmand floating gate 21 are patterned by photolithography and etching, bywhich word lines 11 are formed. At this stage, with the word lines 11used as a mask, an N-type dopant is injected at low energy, by which N⁺diffusion layers 19 are formed in self alignment. After this, depositionof an interlayer insulator, a contact process and a metal process areiteratively performed, by which first bit lines 12 and second bit lines13 are formed.

[0126] In the semiconductor storage device of this embodiment, the areaof one cell is 4F², smaller than that of the conventional AND typememory cell array. Therefore, higher integration becomes implementable,the product yield improves, and the manufacturing cost can be reduced.

[0127] Also, in the case where the memory that is the semiconductorstorage device of this embodiment, a logic circuit and other memories(DRAM, SRAM, etc.) are compositely mounted, the degree of integration ofthe integrated circuit can be enhanced and functional improvement can beachieved.

[0128] (Second Embodiment)

[0129] This embodiment is described below with reference to FIGS. 6 and7.

[0130] The structure of the semiconductor storage device of thisembodiment differs from the semiconductor storage device of theforegoing first embodiment only in the structure of the well region.FIG. 6 is a sectional view as taken along the cut-plane line B-B′ ofFIG. 1. An N-type deep well region 25 and a P-type shallow well region26 are formed in a silicon substrate 17. This well region 26 ispartitioned into a plurality by device isolation regions 16. The deviceisolation regions 16 are set to such a depth that both-side P-typeshallow well regions 26 sandwiching a device isolation region 16 areelectrically isolated from each other. Each of the partitioned wellregions 26 extends meandering in the lateral direction in FIG. 1 as inthe first embodiment. These partitioned well regions 26, as describednext, serve as third bit lines, respectively.

[0131] Next, circuit construction of this embodiment is explained withreference to FIG. 7. The circuit construction of this embodiment differsfrom the circuit construction of the first embodiment in that theshallow well region 26 of each memory cell forms a third bit line. Thisthird bit line connects shallow well regions of memory cells connectedin parallel to a pair of bit lines composed of first bit line and secondbit line. A selector transistor is connected to this third bit line. InFIG. 7, for example, a first third bit line is expressed as Bw1, and aselector transistor corresponding to that is expressed as STBw1.

[0132] In the already-described first embodiment, erase operation on a1-bit basis is impossible. As for the reason of this, since the wellregion and the source/drain region cannot be put into a forward-biasedstate therebetween (PN forward current flows), it is impossible to applysuch a bias that only one bit is selectively chosen in the case wherethe well region is shared by all the memory cells. However, in thisembodiment, the additional provision of the third bit line makes the1-bit basis erase implementable. Referring to FIG. 7, for an eraseoperation of only the memory cell M12, a positive voltage (e.g., 10 V)is applied to the word line W2, a negative voltage (e.g., −8 V) isapplied to the second bit line Bb1, and the selector transistor STBb1 isturned on. In this case, the selector transistor STBa1 is turned off(where the drain region is open). In this case, further, −8 V is appliedto the third bit line Bw1, and the selector transistor STBw1 is turnedon. Now, the ground voltage is applied, for example, to the other thirdbit line and the other first bit line, so that their respective selectortransistors are turned on. By doing so, a high voltage is applied onlyto between the control gate of the memory cell M12 and the P-typeshallow well region, so that electrons are injected from the P-typeshallow well region to the floating gate by FN tunneling, by which thememory cell M12 is erased singly.

[0133] An important thing in this embodiment is that the well region ispartitioned into a plurality and the third bit line is provided. By theprovision of the third bit line, it becomes implementable to perform thewrite, erase and read operations with only 1 bit selected at random.

[0134] As in the first embodiment, it is also possible that the memory,which is this embodiment, and the logic circuit are compositely mountedon one integrated circuit. It is further possible that other memories(DRAM, SRAM, etc.) are also mounted in addition to the memory, which isthis embodiment, and the logic circuit. In that case, larger areas canbe allocated for the logic circuit or other memories in proportion tothe decrease of the area occupied by the memory that is this embodiment,making it possible to achieve functional improvement. Otherwise, largerstorage capacity can be allocated for the memory that is thisembodiment. In that case, for example, it becomes implementable to writea large-scale program temporarily, hold the program even after theturn-off of power, and execute the program also after the reentry ofpower, and moreover to replace the program with another program.

[0135] The fabrication procedure of the semiconductor storage device ofthis embodiment differs from the fabrication procedure of thesemiconductor storage device of the first embodiment in that two stepsfor the formation of the N-type deep well region 25 and the formation ofthe P-type shallow well region 26 are required in the formation of thewell region. The junction depth between the N-type deep well region 25and the P-type shallow well region 26 is determined depending on theinjection conditions (injection energy and injection amount) of dopantsand subsequent thermal processes (annealing process, thermal oxidationprocess, etc.). These dopant injection conditions and thermal processconditions, as well as the depth of the device isolation regions 16 areset so that the P-type shallow well regions 26 are isolated from eachother by the device isolation regions 16.

[0136] In this embodiment, the area of one cell is 4F², smaller thanthat of the conventional AND type memory cell array. Therefore, higherintegration becomes implementable, the product yield improves, and themanufacturing cost can be reduced.

[0137] Furthermore, in this embodiment, 1-bit basis erase is enabled,and the random access is enabled. Thus, there are no restrictions on theaccess method, so that the application to products is facilitated.

[0138] Also, in the case where the memory that is the semiconductorstorage device of this embodiment, a logic circuit and other memories(DRAM, SRAM, etc.) are compositely mounted, the degree of integration ofthe integrated circuit is enhanced and functional improvement becomesachievable.

[0139] (Second-a Embodiment)

[0140] This embodiment is described below with reference to FIG. 8. Thestructure of this embodiment differs from the foregoing secondembodiment in that fine particles (hereinafter, referred to as “discretedots”) 32 composed of a semiconductor or conductor having a size of thenanometer (nm) order are used as a floating gate (FIG. 8). The discretedots 32 are formed into scattered dots on a tunnel oxide film 23, andcovered with a silicon oxide film 33 as a dielectric film. The discretedots 32 may be either arrayed regularly or arranged randomly. Further,the discrete dots may also be arrayed three-dimensionally, for example,other discrete dots may be arranged just above the discrete dots via adielectric film. On the circuit diagram, the case is entirely the samewith the second embodiment (FIG. 7). It is noted here that examples ofthe discrete dots include silicon fine particles, metal fine particlesand the like.

[0141] In a structure where the well region is in common as in the firstembodiment, it is impossible to perform write operations onto memorycells using the discrete dots 32 as the floating gate. As for the reasonof this, since a high voltage is applied to between the control gate andthe drain region in the write operation, only electrons close to thedrain region are pulled out. However, by the well region separated andused as the third bit lines, it becomes implementable to performselective write and selective erase operations also for memory cellsusing the discrete dots 32 as the floating gate. This is because thethird bit lines are formed of the partitioned shallow well regions 26,and independent voltages can be given thereto, respectively.

[0142] An operation example with the discrete dots 32 used as thefloating gate is explained below. Referring to FIG. 7, for a writeoperation into the memory cell M12, a negative voltage (e.g., −8 V) isapplied to the word line W2, a positive voltage (e.g., 6 V) is appliedto the first bit line Ba1, the second bit line Bb1 and the third bitline Bw1, and further the selector transistors STBa1, STBb1 and STBw1are turned on. That is, −8 V is applied to the control gate of thememory cell M12, and 6 V is applied to the source region, the drainregion and the P-type shallow well regions (FIG. 8). In this case, theground voltage is applied, for example, to the other first bit line,second bit line and third bit line, so that their respective selectortransistors are turned on. By doing so, a high voltage is applied onlyto between the control gate of the memory cell M12 and the sourceregion, drain region and P-type shallow well region, so that electronsare subjected to FN tunneling through the oxide film 33. That is,electrons are pulled out from the discrete dots 32 or a charge-trappingfilm, by which the write operation is accomplished. It is noted that forerasing the memory cell M12, it is appropriate to apply a high voltageonly to between the control gate and the source region, drain region andP-type shallow well region. That is, it is appropriate to apply apositive voltage (e.g., 10 V) to the control gate and apply a negativevoltage (e.g., −6 V) to the source region, drain region and P-typeshallow well region. Thus, 1-bit basis erase is enabled also on memorycells using discrete dots as the floating gate or memory cells using afilm that traps electric charges.

[0143] It is noted that the set voltages of individual nodes for write,erase and read operations are not limited the above voltages. In thecase of a memory membrane structure using direct tunneling, the setvoltages for individual nodes can be set lower than those of theabove-described example.

[0144] Next, the procedure for fabricating the semiconductor storagedevice of this embodiment is explained. The fabrication procedure ofthis embodiment differs from the fabrication procedure of the secondembodiment only in the formation of the floating gate. That is, afterthe tunnel oxide film 23 is formed, silicon fine particles are formed byLPCVD (Low Pressure Chemical Vapor Deposition) process and accumulatedon the tunnel oxide film 23, by which discrete dots 32 are formed.Thereafter, an oxide film 33 is formed by CVD process. After this on,the same fabrication procedure as in the second embodiment is applied.

[0145] In the semiconductor storage device of this embodiment, there areadvantages as shown below as compared with the semiconductor storagedevice of the second embodiment.

[0146] When discrete dots are used as the floating gate, the leakage ofstorage charges is reduced as compared with the flash memory. Therefore,device reliability can be improved. Also, in the case where quantum dotmemory, which is one mode of memory using discrete dots, directtunneling can be used for write and erase operations, so that devicedeterioration can be suppressed and its reliability can be improved.

[0147] (Second-b Embodiment)

[0148] This embodiment is explained below with reference to FIG. 9. Thestructure of the semiconductor storage device of this embodiment differsfrom the semiconductor storage device of the foregoing second embodimentin that a charge-trapping film 34 is used instead of the floating gate(FIG. 9). On the circuit diagram, the case is absolutely the same withthe second embodiment (FIG. 7).

[0149] In this embodiment, it is implementable to perform selectivewrite and selective erase operations for memory cells using thecharge-trapping film instead of the floating gate, for the same reasonsas described in the foregoing second-a embodiment. In this case, thecharge-trapping film is, for example, Si₃N₄/SiO₂ film, SiO₂/Si₃N₄/SiO₂film (ONO film) and devices using this are exemplified by, for example,MNOS, SNOS and SONOS. Although silicon nitride is expressed as Si₃N₄ andsilicon oxide as SiO₂, yet their component ratios are not limited bythese expressions. Also, ferroelectric memory film having hysteresischaracteristics may also be used instead of the charge-trapping film.

[0150] An operation example in which the charge-trapping film is usedinstead of the floating gate may be similar to that described in thesecond-a embodiment. It is preferable, however, that the set voltages ofindividual nodes for write, erase and read operations are given byoptimum values according to the charge-trapping film.

[0151] Next, the procedure for fabricating the semiconductor storagedevice of this embodiment is explained. The fabrication procedure ofthis embodiment differs from the fabrication procedure of the secondembodiment only in that a charge-trapping film is formed instead of thefloating gate. The charge-trapping film may be fabricated by acombinational process of thermal oxidation process and CVD filmdeposition process.

[0152] When discrete dots are used as the floating gate, the leakage ofstorage charges is reduced as compared with the flash memory. Therefore,device reliability can be improved.

[0153] (Third Embodiment)

[0154] This embodiment relates to a semiconductor storage device inwhich the semiconductor storage device of the second embodiment or thesecond-a embodiment or the second-b embodiment is incorporated, but inwhich the ratio of a voltage applied to the memory-functional film of aselected memory cell to a voltage applied to the memory-functional filmof non-selected memory cells is set to the largest possible one.

[0155] Generally, in write or erase operation on memory cells, a largevoltage is applied to the memory-functional film of the selected memorycell. Then, some extent of voltage would inevitably be applied also tothe memory-functional film of non-selected memory cells. Therefore, forprevention of malfunction, it is preferable that the ratio of a voltageapplied to the memory-functional film of a selected memory cell to amaximum value of voltages applied to the memory-functional film ofnon-selected memory cells is made as large as possible.

[0156] In a commonly practiced method, for example, for an eraseoperation, the voltage of a selected word line is set to V_(DD), and thevoltage of a selected bit line is set to ground voltage, and the voltageof the other word lines and bit lines is set to V_(DD)/2. In this case,the voltage of V_(DD) is applied to the memory-functional film ofselected memory cell, while the voltage of 0 or V_(DD)/2 is applied tothe memory-functional film of non-selected memory cells. In this case,the ratio of the voltage applied to the memory-functional film of aselected memory cell to the maximum value of voltages applied to thememory-functional film of non-selected memory cells is 2.

[0157] Applied voltages to individual word lines and bit lines for writeand erase operations in the semiconductor storage device of thisembodiment are shown in Table 1. For a write operation, a voltage of 0is applied to a selected word line, (1−A)×V_(DD) is applied tonon-selected word lines, V_(DD) is applied to a selected bit line, andA×V_(DD) is applied to non-selected bit lines. Also, for an eraseoperation, a voltage of V_(DD) is applied to a selected word line,A×V_(DD) is applied to non-selected word lines, 0 is applied to aselected bit line, and (1−A)×V_(DD) is applied to non-selected bitlines. In this case, it holds that 1/3≦A<1/2 (where a case with A=1/2 isthe above-shown commonly practiced case). The ratio of the voltageapplied to the memory-functional film of a selected memory cell to themaximum value of voltages applied to the memory-functional films ofnon-selected memory cells becomes a maximum of 3 (in absolute value)when A=1/3. Thus, the setting of A=1/3 is most preferable.

[0158] Table 1:

[0159] Write: Bit line (Selected) (Non-Selected) Word line V_(DD) A ×V_(DD) (Selected) 0 Voltage applied to Voltage applied to film: film:−V_(DD) −A × V_(DD) (Non-Selected) Voltage applied to Voltage applied to(1 − A) × V_(DD) film: film: −A × V_(DD) (1 − 2A) × V_(DD)

[0160] Erase: Bit line (Non-Selected) Word line (Selected) 0 (1 − A) ×V_(DD) (Selected) Voltage applied to Voltage applied to V_(DD) film:film: V_(DD) A × V_(DD) (Non-Selected) Voltage applied to Voltageapplied to A × V_(DD) film: film: A × V_(DD) (2A − 1) × V_(DD)

[0161] A specific value for V_(DD) may be determined optimally accordingto film quality or film structure. In more detail, it is preparatorilyset that injection or ejection of charges occurs when the absolute valueof the voltage applied to the memory-functional film is V_(DD), whileinjection or ejection of charges does not occur when the absolute valueof the voltage applied to the memory-functional film is A×V_(DD). Inaddition, for a read operation, the voltage applied to thememory-functional film is preferably set to not more than A×V_(DD), inwhich case there never occurs destruction of storage due to the readoperation.

[0162] In this embodiment, the ratio of the voltage applied to thememory-functional film of selected memory cell to the maximum value ofvoltages applied to the memory-functional film of non-selected memorycells is a large one, so that a memory having large operational margincan be implemented.

[0163] (Fourth Embodiment)

[0164] This embodiment is described below with reference to FIG. 10.

[0165] The semiconductor storage device of this embodiment differs fromthe semiconductor storage devices of the first, second, second-a,second-b and third embodiments in that an SOI (Silicon on Insulator)substrate is used instead of the silicon substrate 17 of thesemiconductor storage device of any one of those foregoing embodiments.This SOI substrate 37 has a body 36 made of silicon and provided on thesilicon substrate 17 via a buried oxide film 35. A plan view of thesemiconductor storage device of this embodiment is the same as FIG. 1.FIG. 10 is a schematic view of a cross section of a memory cell in thesemiconductor storage device of this embodiment (shown is a case inwhich a sheet-like floating gate is used). When the body 36 on theburied oxide film 35 is provided as a common body, the resultingoperation is similar to that of the first embodiment. On the other hand,when independent voltages are respectively given to a plurality ofbodies 36 partitioned by the device isolation regions 16 for use asthird bit lines, it becomes possible to execute random access as in thesecond, second-a, second-b and third embodiments. The floating gate 21may be given by discrete dots or a charge-trapping film or by aferroelectric film having hysteresis. Although FIG. 10 shows a case ofthe completely depletion type, yet a partially depletion type may alsobe adopted. In that case, the resistance of the body that becomes thethird bit line can be reduced, allowing higher speed of the device to beimplemented.

[0166] Next, the procedure for fabricating the semiconductor storagedevice of this embodiment is explained. First, device isolation regions16 are formed in the SOI substrate 37. Subsequently, dopant injectioninto the body 35 is performed so that the memory device has a properthreshold. The formation of upper structure after this is the same as inthe procedure of formation of the first, second, second-a and second-bembodiments.

[0167] In this embodiment, the following effects can be obtained inaddition to the effects obtained by the first, second, second-a,second-b and third embodiments. In this embodiment, for the presence ofthe thick buried oxide film 35, the electrostatic capacity between thebody 36 and the silicon substrate 17 can be made very small. Incontrast, in the second, second-a, second-b and third embodiments, theelectrostatic capacity between the shallow well region 26 and the deepwell region 25 is quite large. Also, with the use of the SOI substrate37, the junction capacity between the N⁺ active layers 19 and the body36 can be made quite small. As a result of this, in this embodiment, theconsumption current for charging the capacity can be made small.Furthermore, with the use of the SOI substrate 37, the depth of the N⁺active layers 19 can be easily made shallower, so that the short-channeleffect can be suppressed and a micro-finer device can be implemented.From the above reasons, the use of the SOI substrate makes it feasibleto achieve power consumption reduction and micro-fining.

[0168] (Fifth Embodiment)

[0169] The semiconductor storage device of this embodiment is describedwith reference to FIGS. 11 to 17. FIG. 11 is a schematic view showing aplanar pattern of the memory cell array in the semiconductor storagedevice of this embodiment. FIG. 12 is a sectional view as taken along aline G-G′ of FIG. 11, and FIG. 13 is a sectional view as taken along aline H-H′ of FIG. 11. Further, FIGS. 14 to 16 show a modification of thememory cell array shown in FIGS. 11 to 13. FIG. 14 is a schematic viewshowing a planar pattern, FIG. 15 is a sectional view as taken along aline I-I′ of FIG. 14, and FIG. 16 is a sectional view as taken along aline J-J′ of FIG. 14. FIG. 17 is a circuit diagram of the semiconductorstorage device shown in FIGS. 11 to 16.

[0170] First, constitution of the semiconductor storage device of thisembodiment is explained with reference to FIGS. 11 to 13. As shown inFIGS. 12 and 13, a P-type well region 42 is formed in a siliconsubstrate 41. Further, a plurality of device isolation regions 43 areformed and arrayed at a pitch of 2F (where F is a minimum machiningpitch) so as to extend linearly in one direction (lateral direction inFIG. 11) as shown by hatching in FIG. 11. As a result of this, as shownin FIG. 12, silicon active regions are formed so as to extend laterallyin upper part of the P-type well region 42 and to be sandwiched byneighboring device isolation regions 43. The device isolation regions 43are set to such a depth that next-described N⁺ diffusion layers 44 areelectrically isolated from each other but that the P-type well region 42is not electrically isolated.

[0171] In upper part of the P-type well region 42 are formed N⁺diffusion layers 44 as a dopant diffusion region. Each of the N⁺diffusion layers 44 functions as a source region or drain regionaccording to the selection by bit lines during the use of this memory. Aplurality of word lines 45 composed of an electrical conductor such asdopant-introduced polysilicon, polycide or metal are formed so as toextend straight in the vertical direction (longitudinal direction inFIG. 11) against the direction of the device isolation regions 43. Thesilicon active regions located under the word lines 45 (upper portion ofthe well region 42) are channel regions. These channel regions and theword lines 45 are isolated from each other by a multilayered filmcomposed of a floating gate 46 and silicon oxide film 47. On thischannel region, the word line 45 serves as a control gate.

[0172] Plate electrodes 48 composed of dopant-introduced polysilicon,polycide, metal or the like cover the top of the N⁺ diffusion layers 44,the top of the device isolation regions 43 and the top of the word lines45 other than plate electrode holes 49 (see FIG. 11). Then, the plateelectrodes 48 are electrically connected to one of the source region andthe drain region in the N⁺ diffusion layers 44. Also, the plateelectrodes 48 and the word lines 45 are electrically isolated from eachother by a dielectric film 50. A plurality of bit lines 51 formed ofmetal are disposed at a pitch of 2F so as to extend straight in avertical direction (lateral direction in FIG. 11) with respect to theword lines 45. A device formation region (top of the well region 42) andan interconnect layer in which the bit lines 51 are formed are isolatedfrom each other by an interlayer insulator 52, while the bit lines 51and the other one of the source region and the drain region areconnected to each other at a pitch of 4F by bit line contacts 53provided at the positions of the plate electrode holes 49. It is notedthat one memory cell is represented by a rectangle 54 depicted bytwo-dot chain line in FIG. 11, its area being 4F².

[0173] The memory cell array may also be formed into shapes shown inFIGS. 14 to 16 (in which the same reference numerals as numerals forcomponent parts in FIGS. 11 to 13 are used). In the case of the memorycell array shown in FIGS. 14 to 16, a plate electrode 48 is strip-shapedand the strip-shaped plate electrodes 48 are arrayed in parallel at apitch of 4F in the same direction as the word lines 45. Then, the bitline contacts 53, which are connected to the other one of the sourceregion and the drain region in regions at which the plate electrodes 48are absent (between the plate electrodes 48), are arrayed linearly at apitch of 2F in a direction along which the word lines 45 extend.

[0174] Next, circuit construction of the semiconductor storage device ofthis embodiment is explained with reference to FIG. 17. The memory cellarray constituting this semiconductor storage device is of the so-calledAND type array. That is, n (n: natural number) memory cells M areconnected in parallel to one bit line B. In FIG. 17, for example, afirst bit line is expressed as B1, and an n-th memory cell connected tothe first bit line B1 is expressed as M1n. Also, n word lines W arearrayed vertically to the bit lines B, respectively, so as to connectcontrol gates 15 of the respective memory cells M to each other. In FIG.17, the word lines are expressed as W1 to Wn. It is noted that one ofthe source region and the drain region is connected to one another by aplate electrode (expressed as Plt).

[0175] Next, an operation example of the semiconductor storage device ofthis embodiment is explained with reference to FIG. 17. As an example,it is assumed that a state of low threshold of each memory cell is awrite state, while a state of high threshold is an erase state. Furtheras an example, it is assumed that the drain region is connected to thebit line B while the source region is connected to the plate electrodePlt. Furthermore, the plate electrode Plt is large in electrostaticcapacity with the other nodes, and so its voltage is desirablymaintained constant. The following description is made on a case wherethe voltage of the plate electrode Plt is set at 0 V at all times, butthe present invention is not limited to this.

[0176] Referring to FIG. 17, for a write operation into a memory cellM12, a negative voltage (e.g., −8 V) is applied to the word line W2, anda positive voltage (e.g., 6 V) is applied to the first bit line B1. Inthis case, the voltage of the plate electrode Plt and the P-type wellregion 42 is set to ground voltage (0 V). By doing so, a high voltage isapplied to between the control gate 45 of the memory cell M12 and drainregion, so that electrons are pulled out from the floating gate 46 tothe drain region by FN (Fowler-Nordheim) tunneling, by which the writeoperation is accomplished.

[0177] On the other hand, an erase operation is performed collectivelyfor all memory cells M on a selected word line. Referring to FIG. 17,for erasing the memory cell M12 and the memory cell M22, a positivevoltage (e.g., 18 V) is applied to the word line W2, and the voltage ofthe plate electrode Pit and the P-type well region 42 is set to groundvoltage (0 V). In this case, the drain region is set open. By doing so,a high voltage is applied to between the control gates 45 of the memorycell M12 and the memory cell M22 and the P-type well region 42, so thatelectrons are injected from the P-type well region 42 to the floatinggate 46 by FN tunneling, by which the erase operation is accomplished.

[0178] In FIG. 17, for a read operation of data of the memory cell M12,a positive voltage (e.g., 3 V) is applied to the word line W2, apositive voltage (e.g., 1 V) is applied to the first bit line B1. Inthis case, the voltage of the plate electrode Plt and the P-type wellregion 42 is set to ground voltage (0 V). By doing so, the data of thememory cell M12 can be read out.

[0179] It is noted that the set voltages of individual nodes for write,erase and read operations are not limited the above voltages.

[0180] Furthermore, it is also possible that the memory, which is thesemiconductor storage device of this embodiment, and the logic circuitare compositely mounted on one integrated circuit. Otherwise, it isfurther possible that other memories (DRAM, SRAM, etc.) are also mountedcompositely in addition to the memory, which is the semiconductorstorage device of this embodiment, and the logic circuit. In that case,larger areas can be ensured for the logic circuit or other memories inproportion to the extent to which the area occupied by the memory thatis the semiconductor storage device of this embodiment can be decreasedas described above, making it possible to achieve functionalimprovement. Otherwise, in proportion to the extend to which the areaoccupied by the memory that is the semiconductor storage device of thisembodiment can be decreased, larger storage capacity can be allocatedfor the memory as the occupation area remains the same as conventional.In that case, for example, it becomes implementable to write alarge-scale program temporarily, hold the program even after theturn-off of power, and execute the program also after the reentry ofpower, and moreover to replace the program with another program.

[0181] Next, the procedure for fabricating the semiconductor storagedevice of this embodiment is explained. First, dielectric deviceisolation regions 43 are formed in the silicon substrate 41, andsubsequently a P-type well region 42 is formed. Thereafter, tunnel oxidefilm is formed by thermal oxidation, and a polysilicon film 46 is formedby CVD (Chemical Vapor Deposition) process. This polysilicon film 46 ispatterned by photolithography and etching, by which a floating gate 46is formed. After that, a silicon oxide film and a polysilicon film 45are formed in order by CVD process. Further, a dielectric film 50 ofsilicon oxide or silicon nitride or the like is formed on thepolysilicon film 45 by CVD process.

[0182] After that, the dielectric film 50, the polysilicon film 45 andthe silicon oxide film are patterned by photolithography and etching, bywhich word lines 45 are formed. In that case, it is also possible thatonly the dielectric film 50 is patterned with the photoresist used as amask, and the polysilicon film 45 and the silicon oxide film arepatterned by etching under the condition that the dielectric film 50patterned after the removal of photoresist is used as a mask. After theword lines 45 are formed in this way, silicon nitride is deposited allover by the CVD process and further etched back, by which side walls ofthe word lines 45 are covered with the dielectric film 50.

[0183] After that, an N-type dopant is injected at low energy with theword lines 45 used as a mask, by which N⁺ diffusion layers 44 are formedin self alignment on the the surface of the P-type well region 42. Afterthis, a polysilicon film 48 is deposited all over and patterned, bywhich plate electrodes 48 are formed. Then, deposition of an interlayerinsulator 52, a contact process and a metal process are performed, bywhich bit lines 51 are formed.

[0184] As described above, in this embodiment, the bit lines 51 and theplate electrodes 48, which are alternately connected to the N⁺ diffusionlayers 44, are formed upward of the P-type well region 42 of the siliconsubstrate 41. Therefore, the bit lines 51 and the plate electrodes 48can be formed in a stacking form by using different interconnect layersisolated by the interlayer insulator 52. As a result, in a planarpattern layout, there is no need for the margin equivalent to a distanceof 1F to which the source line 2 and the bit line 3 formed of anidentical dopant diffusion layer in the semiconductor substrate areisolated from each other as has been in the conventional semiconductorstorage device shown in FIG. 32. Further, within the silicon activeregions sandwiched by the device isolation regions 43 and extendinglinearly, the N⁺ diffusion layers 44 formed on both sides of each wordline 45 perpendicular to the device isolation regions 43 (i.e., the N⁺diffusion layers 44 neighboring each other via each channel region)serve as a source region and a drain region of an FET as they are pairedrespectively. That is, each of the N⁺ diffusion layers 44 is shared bytwo FETs. Thus, N⁺ diffusion layers 44 corresponding to a width of 1F inconventional one memory cell shown in FIG. 32 become unnecessary. As aconsequence of the above, the longer side of a 4F×2F (=8F²) memory celldepicted by two-dot chain line in FIG. 32 is shortened by an extent of2F as described below. Thus, the size of the memory cell becomes 2F×2Fas shown by two-dot chain line in FIG. 11 and FIG. 14, and its area canbe made 4F², smaller than 6F² of the NAND type memory.

[0185] Conclusionally, according to the semiconductor storage device ofthis embodiment, erase operation on the word line basis is enabled as inthe conventional AND type memory cell array, its read speed is alsocomparable thereto, and moreover the area of one memory cell can be madesmaller than that of the conventional AND type memory cell array.Therefore, higher integration becomes implementable, the product yieldimproves, and the manufacturing cost can be reduced.

[0186] Also, in the case where the memory that is the semiconductorstorage device of this embodiment, a logic circuit and other memories(DRAM, SRAM, etc.) are compositely mounted to make up an integratedcircuit, the degree of integration of the integrated circuit can beenhanced and functional improvement can be achieved.

[0187] (Sixth Embodiment)

[0188] This embodiment is explained with reference to FIGS. 18 to 22.The semiconductor storage device of this embodiment differs from that ofthe foregoing fifth embodiment in the structure of well region. FIGS. 18and 19 are sectional views of a memory cell array in the semiconductorstorage device of this embodiment, corresponding to FIGS. 12 and 13 inthe fifth embodiment. Further, FIGS. 20 and 21 are also sectional viewsof a memory cell array in the semiconductor storage device of thisembodiment, corresponding to FIGS. 15 and 16 in the fifth embodiment.

[0189] Referring to FIGS. 18 and 19, an N-type deep well region 62 andP-type shallow well regions 63 are formed in a silicon substrate 61.Device isolation regions 64 are set to such a depth that both-sideP-type shallow well regions 63 sandwiching a device isolation region 64are electrically isolated from each other. That is, an array of elongateP-type shallow well regions 63 is formed at a pitch of 2F, and these areelectrically isolated from each other by the device isolation regions64. These P-type shallow well regions 63, which are arrayed along thesame direction as first bit lines 65 corresponding to the bit lines 51of the fifth embodiment, can be made to serve as second bit lines.

[0190] It is noted that N⁺ diffusion layers 66, word lines 67, floatinggate 68, silicon oxide film 69, plate electrodes 70, dielectric film 71,interlayer insulator 72 and bit line contacts 73 in FIGS. 18 and 19 areidentical to the N⁺ diffusion layers 44, the word lines 45, the floatinggate 46, the silicon oxide film 47, the plate electrodes 48, thedielectric film 50, the interlayer insulator 52 and the bit linecontacts 53, respectively, in FIGS. 12 and 13 of the fifth embodiment.

[0191] In the memory cell array shown in FIGS. 20 and 21, as in the caseof the memory cell array shown in FIGS. 14 to 16 of the fifthembodiment, the plate electrodes 70 are strip-shaped (see FIG. 14), andthese strip-shaped plate electrodes 70 are arrayed in parallel at apitch of 4F along the same direction as the word lines 67. Then, the bitline contacts 73, which are connected to one of the source region andthe drain region in regions at which the plate electrodes 70 are absent(between the plate electrodes 70), are arrayed linearly at a pitch of 2Fin a direction along which the word lines 67 extend. The rest of thememory cell array being similar to the memory cell array shown in FIGS.18 and 19, an N-type deep well region 62 and a P-type shallow wellregions 63 are formed in the silicon substrate 61, and the P-typeshallow well regions 63 constitute second bit lines.

[0192] Next, circuit construction of the semiconductor storage device ofthis embodiment is explained with reference to FIG. 22. The memory cellarray constituting this semiconductor storage device differs from thememory cell array shown in FIG. 17 of the fifth embodiment in that theshallow well region in each memory cell forms a second bit line. Thissecond bit line Bw is paired with a first bit line Ba to form a bit linepair, and memory cells M are connected in parallel to this bit linepair, forming a so-called AND type array. It is noted that in FIG. 22,for example, a first bit line is expressed as Ba1 and a first second bitline is expressed as Bw1. The rest of the circuit construction is thesame as in the memory cell array shown in FIG. 17 of the fifthembodiment.

[0193] By comparison, the circuit construction of the fifth embodimentis incapable of random access (1-bit basis write and erase operations).As for the reason of this, since the well region 42 and the source/drainregion 44 cannot be put into a forward-biased state therebetween (PNforward current flows), it is impossible to apply such a bias that onlyone bit is selectively chosen in the case where the well region 42 isshared by all the memory cells M. However, in the case of the memorycell array of this embodiment, the additional provision of the secondbit lines Bw makes the 1-bit basis write and erase implementable.

[0194] Further, in order to reduce the leakage of storage charges fromthe floating gate 68 of the memory cell M, the floating gate 68 in somecases may be formed of discrete dots or a charge-trapping film. However,in the case where the well region 42 is in common to all the memorycells M as in the foregoing fifth embodiment, it is impossible toperform write operations with the use of discrete dots or acharge-trapping film as the floating gate 46. As for the reason of this,since a high voltage is applied only to between the control gate 45 andthe drain region 44 in the write operation, only electrons close to thedrain region 44 are pulled out because of the unlikeliness of leakage ofstorage charges, conversely unfortunately. However, with the shallowwell region 63 separated by the device isolation regions 64 and the deepwell region 22 and used as the second bit lines Bw as in thisembodiment, it becomes implementable to perform selective write andselective erase operations also for memory cells using discrete dots ora charge-trapping film as the floating gate 68. This is because theshallow well regions 63 are formed into independent second bit lines Bwand independent voltages can be given to the shallow well regions 63 ofthe individual memory cells M, respectively.

[0195] In this embodiment, by virtue of the use of a bulk substrate, alarge degree of freedom is allowed for the design of the shallow wellregions 63 constituting the second bit lines Bw, so that depth anddopant level of the shallow well regions 63 can be set freely.Therefore, it becomes possible to provide a sufficient depth of theshallow well regions 63, provide a relatively light dopant level ofproximities (channel regions) to the surface of the shallow well regions63 for obtainment of a proper threshold for the device, and provide aheavy dopant level at relatively deep regions of the shallow wellregions 63. By doing so, the resistance of the shallow well regions 63can be made low, so that the memory can be operated at high speed.

[0196] An important thing in this embodiment is that the well region isseparated into the deep well region 62 and the shallow well region 63,by which the second bit line Bw formed of the shallow well region 63 isprovided. By the provision of this second bit line Bw, it becomesimplementable to perform the write, erase and read operations with only1 bit selected at random. Further, as detailed later, it also becomespossible to use discrete dots or a charge-trapping film as the floatinggate 68.

[0197] As in the case of the semiconductor storage device of the fifthembodiment, it is also possible that the memory, which is thesemiconductor storage device of this embodiment, and the logic circuitare compositely mounted on one integrated circuit. Otherwise, it isfurther possible that other memories (DRAM, SRAM, etc.) are also mountedcompositely in addition to the memory, which is the semiconductorstorage device of this embodiment, and the logic circuit. In that case,larger areas can be ensured for the logic circuit or other memories inproportion to the extent to which the area occupied by the memory thatis the semiconductor storage device of this embodiment can be decreasedas described above, making it possible to achieve functionalimprovement. Otherwise, in proportion to the extend to which the areaoccupied by the memory that is the semiconductor storage device of thisembodiment can be decreased, larger storage capacity can be allocatedfor the memory as the occupation area remains the same as conventional.In that case, for example, it becomes implementable to write alarge-scale program temporarily, hold the program even after theturn-off of power, and execute the program also after the reentry ofpower, and moreover to replace the program with another program.

[0198] Next, the procedure for fabricating the semiconductor storagedevice of this embodiment is explained. The fabrication procedure of thesemiconductor storage device of this embodiment differs from thefabrication procedure of the semiconductor storage device of the fifthembodiment in that two steps for the formation of the N-type deep wellregion 62 and the formation of the P-type shallow well region 63 arerequired in the formation of the well region. The junction depth betweenof the N-type deep well region 62 and the P-type shallow well region 63is determined depending on the injection conditions (injection energyand injection amount) of dopants and subsequent thermal processes(annealing process, thermal oxidation process, etc.). These dopantinjection conditions and thermal process conditions, as well as thedepth of the device isolation regions 64 need to be set so that theP-type shallow well regions 63 are isolated from each other by thedevice isolation regions 64.

[0199] In the semiconductor storage device of this embodiment, as in thecase of the fifth embodiment, the area of one cell is 4F², smaller thanthat of the conventional AND type memory cell array. Therefore, higherintegration becomes implementable, the product yield improves, and themanufacturing cost can be reduced.

[0200] Furthermore, in the case of the semiconductor storage device ofthis embodiment, 1-bit basis erase is enabled, and the random access isenabled. Thus, there are no restrictions on the access method, so thatthe application to products is facilitated.

[0201] Furthermore, in the semiconductor storage device of thisembodiment, it becomes possible to use discrete dots or acharge-trapping film as the floating gate 68. Therefore, low voltagedrive or the like is enabled so that a memory characteristic improvementbecomes achievable.

[0202] Still further, in the semiconductor storage device of thisembodiment, since the depth and dopant level of the shallow well regions63 can be set freely by virtue of the use of a bulk substrate, itbecomes easier to lower the resistance of the shallow well regions 63,making it easier to raise the signal transfer of the second bit linesBw, so that the memory can be operated at high speed.

[0203] Also, in the case where the memory that is the semiconductorstorage device of this embodiment, a logic circuit and other memories(DRAM, SRAM, etc.) are compositely mounted to form an integratedcircuit, the degree of integration of the integrated circuit can beenhanced and functional improvement can be achieved.

[0204] Now write and erase operations of the semiconductor storagedevice of this embodiment are explained below with reference to FIG. 22.As an example, it is assumed that a state of low threshold of the memorycell is a write state, while a state of high threshold is an erasestate.

[0205] First, for a write operation into the memory cell M12, a negativevoltage (e.g., −14 V) is applied to a selected word line W2, and aground voltage (0 V) is applied to selected first bit line Ba1 andsecond bit line Bw1. In this case, the selected first bit line Ba1 maybe set open. The plate electrode Pit is set to ground voltage (0 V). Anegative voltage (e.g., −7 V) is applied to non-selected word lines Wand second bit lines Bw. By doing so, a high voltage is applied only tobetween the control gate 67 of the memory cell M12 and the P-typeshallow well region 63, so that electrons are ejected from the floatinggate 68 to the channel region by FN tunneling, by which the 1-bit writeoperation is accomplished.

[0206] On the other hand, for erasing the memory cell M12, a positivevoltage (e.g., 9 V) is applied to the selected word line W2, a negativevoltage (e.g., −9 V) is applied to the selected first bit line Ba1, anda negative voltage (e.g., −9 V) is applied to the selected second bitline Bw1. In this case, the plate electrode Plt is set to ground voltage(0 V). The ground voltage (0 V) is applied to non-selected word lines Wand second bit lines B. By doing so, a high voltage is applied only tobetween the control gate 67 of the memory cell M12 and the P-typeshallow well region 63, so that electrons are injected from the channelregion to the floating gate 68 by FN tunneling, by which the 1-bit eraseoperation is accomplished. The set voltages of individual nodes forwrite and erase operations are not limited the above voltages.

[0207] Furthermore, the injection and ejection of electrons may occurfrom the control gate (word line) 67 side. In that case, for example, asshown in FIG. 23, the film thickness of the dielectric film (siliconoxide film) 69 between the channel region and the floating gate 68 mayappropriately be set thicker than the film thickness of the dielectricfilm between the floating gate 68 and the control gate 67. For instance,the film thickness of the dielectric film 69 is set to 7 nm to 15 nm,and the film thickness of the dielectric film between the floating gate68 and the control gate 67 is set to 3 nm to 10 nm. Otherwise, thematerial of the dielectric film between the floating gate 68 and thecontrol gate 67 may be given by a material which is relatively lower inbarrier than the dielectric film 69. For instance, when the dielectricfilm 69 is formed of oxide and the dielectric film between the floatinggate 68 and the control gate 67 is formed of silicon nitride, electriccharges can be injected and ejected from the control gate 67 side to thefloating gate 68 even with the two dielectric films equal in thicknessto each other. It is noted here that, the cross section of the memorycell is schematically represented in FIG. 23, where the direction of thedevice isolation regions 64 is depicted in a way different from theactual one and the silicon substrate 61 is omitted.

[0208] Further, the above-described operation method can be applied alsoto the case where the injection and ejection of electrons occurs fromthe control gate (word line) 67 side. However, write operation and eraseoperation are reversed relative to the foregoing case where theinjection and ejection of electrons occurs from the channel region side.

[0209] By operating the semiconductor storage device of this embodimentin the way described above, it becomes implementable to perform randomaccess.

[0210] (Seventh Embodiment)

[0211] This embodiment relates to a semiconductor storage device inwhich fine particles (hereinafter, referred to as “discrete dots”)composed of a semiconductor or conductor having a size of the nanometer(nm) order are used as the floating gate 8 in the semiconductor storagedevice of the foregoing sixth embodiment. The basic structure of thememory cell array in the semiconductor storage device of this embodimentis similar to that of FIGS. 18 and 19 or FIGS. 20 and 21. Also, itscircuit diagram is entirely the same as that of FIG. 22. Therefore, thedescription of basic structure and circuit operation of the memory cellarray is omitted.

[0212]FIG. 24 is a schematic sectional view of a memory cell M12 in amemory cell array corresponding to FIG. 23 of the sixth embodiment.N-type deep well region 81, P-type shallow well region 82, deviceisolation regions 83, N⁺ diffusion layers 84, control gate 85, word lineW2, first bit line Ba1, second bit line Bw1 and plate electrode Plt areidentical to the N-type deep well region 62, the P-type shallow wellregions 63, the device isolation regions 64, the N⁺ diffusion layers 66,the control gate 67, the word line W2, the first bit line Ba1, thesecond bit line Bw1 and the plate electrode Plt, respectively, in FIG.23 of the foregoing sixth embodiment.

[0213] At an intermediate portion between the channel region and thecontrol gate 85 in a dielectric film (silicon oxide film) 87 thatseparates the channel region of the P-type shallow well region 82 andthe control gate 85 from each other, discrete dots 86 that serve as thefloating gate are formed in a scattered form. In this case, the discretedots 86 is exemplified by dots of a conductor or semiconductor formed ina discrete manner in the dielectric film 87. For example, silicon dotsor metal dots formed in silicon oxide film can be mentioned.

[0214] Operation of the memory cell array using the discrete dots 86 asthe floating gate is explained below. In the following description, asan example, it is assumed that a state of low threshold of the memorycell M is a write state, while a state of high threshold is an erasestate, and that the injection and ejection of electrons occurs from thechannel side. In addition, write operation and erase operation arereversed when the injection and ejection of electrons occurs from thecontrol gate (word line W) 85 side.

[0215] Referring to FIG. 24, for a write operation into the memory cellM12, a negative voltage (e.g., −6 V) is applied to the word line W2, anda ground voltage (0 V) is applied to the first bit line Ba1 and thesecond bit line Bw1. In this case, the plate electrode Plt is set toground voltage (0 V). That is, −6 V is applied to the control gate 85 ofthe memory cell M12, and 0 V is applied to the source region and theP-type shallow well region 82. In this case, a negative voltage (e.g.,−3 V) is applied to non-selected word lines, the first and second bitlines. By doing so, a high voltage is applied only to between thecontrol gate 85 of the memory cell M12 and the source/drain region andP-type shallow well region 82 connected to the first bit line Ba1, bywhich the write operation is accomplished.

[0216] Further, for erasing the memory cell M12, it is appropriate toapply a high voltage only to between the control gate 85 of the memorycell M12 and the source/drain region and P-type shallow well region 82connected to the first bit line Ba1. That is, it is appropriate that apositive voltage (e.g., 3 V) is applied to the selected word line W2while a negative voltage (e.g., −3 V) is applied to the source/drainregion (selected first bit line Ba1) and P-type shallow well region(selected second bit line Bw1) connected to the first bit line Ba1.Thus, it becomes implementable to perform write and erase operations onthe 1-bit basis also for memory cells using the discrete dots 86 as thefloating gate. Also, for a read operation, for example, it isappropriate to apply 0 V to the selected word line W2, −1 V to theselected first bit line Ba1, and −1 V to the selected second bit lineBw1.

[0217] It is noted that the set voltages of individual nodes for write,erase and read operations are not limited to the above voltages. In thecase of a memory membrane structure using direct tunneling, the setvoltages for individual nodes can be set lower than those of theabove-described example.

[0218] Next, the fabrication procedure of the semiconductor storagedevice of this embodiment is explained. The fabrication procedure of thesemiconductor storage device of this embodiment differs from thefabrication procedure of the sixth embodiment only in the fabricationprocedure of the floating gate. The floating gate in the form ofdiscrete dots can be formed, for example, by the following procedure.

[0219] That is, after the formation of up to the tunnel oxide filmconstituting lower part of the dielectric film 87 in the same manner asin the fabrication procedure of the sixth embodiment, siliconmicrocrystal is formed on the tunnel oxide film by LPCVD process, bywhich discrete dots 86 are formed. After that, oxide film is formed byCVD process. It is noted that the discrete dots 86 may be either arrayedregularly or arranged randomly. Further, the discrete dots 86 may alsobe arrayed three-dimensionally.

[0220] As shown above, according to the semiconductor storage device ofthis embodiment, since the discrete dots 86 are used as the floatinggate, the leakage of storage charges is reduced as compared with theflash memories of the fifth and sixth embodiments in which conductorfilm is used as the floating gate. Therefore, device reliability can beimproved. Also, in the case where quantum dot memory-functional film,which is one mode of memory-functional film using discrete dots 86,direct tunneling can be used for write and erase operations, so thatdevice deterioration can be suppressed by low voltage operation and itsreliability can be improved.

[0221] (Eigth Embodiment)

[0222] This embodiment relates to a semiconductor storage device inwhich discrete dots formed into a plurality of layers are used as thefloating gate 68 in the semiconductor storage device of the foregoingsixth embodiment. The basic structure of the memory cell array in thesemiconductor storage device of this embodiment is similar to that ofFIGS. 18 and 19 or FIGS. 20 and 21. Also, its circuit diagram isentirely the same as that of FIG. 22. Therefore, the description ofbasic structure and circuit operation of the memory cell array isomitted.

[0223]FIG. 25 is a schematic sectional view of a memory cell M12 in amemory cell array corresponding to FIG. 23 of the sixth embodiment.N-type deep well region 91, P-type shallow well region 92, deviceisolation regions 93, N⁺ diffusion layers 94, control gate 95, word lineW2, first bit line Ba1, second bit line Bw1 and plate electrode Plt areidentical to the N-type deep well region 62, the P-type shallow wellregions 63, the device isolation regions 64, the N⁺ diffusion layers 66,the control gate 67, the word line W2, the first bit line Ba1, thesecond bit line Bw1 and the plate electrode Plt, respectively, in FIG.23 of the foregoing sixth embodiment.

[0224] At an intermediate portion between the channel region and thecontrol gate 95 in a dielectric film (silicon oxide film) 98 thatseparates the channel region of the P-type shallow well region 92 andthe control gate 95 from each other, discrete dots 96, 97 that serve asthe floating gate are formed in two layers. According to this structure,double tunnel junction is formed by a tunnel junction formed between thechannel region and the lower-layer discrete dots 97 and a tunneljunction formed between the lower-layer discrete dots 97 and theupper-layer discrete dots 96. Therefore, even if the charge-tunnelingprocess is direct tunneling, a remarkable memory effect can be produced.That is, according to this embodiment, the charge memory effect of thefloating gate can be increased as compared with the seventh embodiment.It is noted that the injection and ejection of electrons may occureither from the channel region side or from the control gate 95 side.

[0225] Furthermore, although the number of layers of discrete dotsconstituting the floating gate has been set to “2” in this embodiment,yet the present invention is not limited to this.

[0226] (Ninth Embodiment)

[0227] This embodiment relates to a semiconductor storage device inwhich a charge-trapping film for trapping electric charges is used asthe floating gate 68 in the semiconductor storage device of theforegoing sixth embodiment. The basic structure of the memory cell arrayin the semiconductor storage device of this embodiment is similar tothat of FIGS. 18 and 19 or FIGS. 20 and 21. Also, its circuit diagram isentirely the same as that of FIG. 22. Therefore, the description ofbasic structure and circuit operation of the memory cell array isomitted.

[0228]FIG. 26 is a schematic sectional view of a memory cell M12 in amemory cell array corresponding to FIG. 23 of the sixth embodiment.N-type deep well region 101, P-type shallow well region 102, deviceisolation regions 103, N⁺ diffusion layers 104, control gate 105, wordline W2, first bit line Ba1, second bit line Bw1 and plate electrode Pltare identical to the N-type deep well region 62, the P-type shallow wellregions 63, the device isolation regions 64, the N⁺ diffusion layers 66,the control gate 67, the word line W2, the first bit line Ba1, thesecond bit line Bw1 and the plate electrode Plt, respectively, in FIG.23 of the foregoing sixth embodiment.

[0229] Between the channel region of the P-type shallow well region 102and the control gate 105 is formed a charge-trapping film 106 thatserves as the floating gate. The semiconductor storage device of thisembodiment is enabled to perform selective write and selective eraseoperations on the 1-bit basis, for the same reason as described in thesixth embodiment.

[0230] In this case, the charge-trapping film 106 is, for example,Si₂N₄/SiO₂ film or SiO₂/Si₂N₄/SiO₂ film (ONO film). Devices using thisare exemplified by, for example, MNOS, SNOS, SONOS or the like. Also,when the ONO film is used, the charge-trapping efficiency is increasedso that memory characteristics can be improved, as compared to when theSi₂N₄/SiO₂ film is used. Although silicon nitride film is given by Si₂N₄and silicon oxide film is given by SiO₂ in this case, yet the individualcomponent ratios are not limited by these. Also, ferroelectric memoryfilm having hysteresis characteristics may also be used instead of thecharge-trapping film 106.

[0231] Operation of the semiconductor storage device using thecharge-trapping film 106 instead of the floating gate is similar to, forexample, the operation of the semiconductor storage device of the sixthembodiment. It is preferable, however, that the set voltages ofindividual nodes for write, erase and read operations are given byoptimum values selected according to the charge-trapping film 106.

[0232] Next, the fabrication procedure of the semiconductor storagedevice of this embodiment is explained. The fabrication procedure of thesemiconductor storage device of this embodiment differs from thefabrication procedure of the sixth embodiment only in the fabricationprocedure of the floating gate. The charge-trapping film 106 can beformed, for example, by the following procedure.

[0233] That is, after the formation of the device isolation regions 103,the N-type deep well region 101 and the P-type shallow well region 102in the same manner as in the fabrication procedure of the sixthembodiment, a charge-trapping film 106 is formed on the P-type shallowwell region 102 instead of the floating gate by a combinational processof thermal oxidation process and CVD film deposition process.

[0234] With a charge-trapping film used for holding of electric charges,the leakage of storage charges is reduced as compared with the flashmemories of the fifth and sixth embodiments in which conductor film isused as the floating gate. Therefore, device reliability can beimproved.

[0235] (Tenth Embodiment)

[0236] This embodiment relates to a semiconductor storage device inwhich a composite member of polysilicon film and multilayered discretedots are used as the floating gate 68 in the semiconductor storagedevice of the foregoing sixth embodiment. The basic structure of thememory cell array in the semiconductor storage device of this embodimentis similar to that of FIGS. 18 and 19 or FIGS. 20 and 21. Also, itscircuit diagram is entirely the same as that of FIG. 22. Therefore, thedescription of basic structure and circuit operation of the memory cellarray is omitted.

[0237]FIG. 27 is a schematic sectional view of a memory cell M12 in amemory cell array corresponding to FIG. 23 of the sixth embodiment.N-type deep well region 111, P-type shallow well region 112, deviceisolation regions 113, N′ diffusion layers 114, control gate 115, wordline W2, first bit line Ba1, second bit line Bw1 and plate electrode Pltare identical to the N-type deep well region 62, the P-type shallow wellregions 63, the device isolation regions 64, the N⁺ diffusion layers 66,the control gate 67, the word line W2, the first bit line Ba1, thesecond bit line Bw1 and the plate electrode Plt, respectively, in FIG.23 of the foregoing sixth embodiment.

[0238] At an intermediate portion between the channel region and thecontrol gate 115 in silicon oxide film 116 that separates the channelregion of the P-type shallow well region 112 and the control gate 115from each other, a polysilicon film 117 is formed on a channel regionside, while discrete dots 118 composed of silicon fine particles areformed on a control gate 115 side via the silicon oxide film 116, andfurther discrete dots 119 composed of silicon fine particles are formedobliquely upward of the discrete dots 118 via the silicon oxide film116.

[0239] Next, characteristics of the memory-functional film having thecomposite-member structure of the polysilicon film 117 and thetwo-layered discrete dots 118, 119 are described. FIGS. 28 and 29 showrelationships between capacity C of the memory-functional film andapplied voltage Vg. That is, the applied voltage Vg is a voltage appliedto the control gate 115 side against the shallow well region 112 side,and C refers to electrostatic capacity per unit area. FIG. 28 shows C-Vgcharacteristics resulting from scanning the applied voltage Vg from +3 Vto −3 V and thereafter scanning the applied voltage Vg again to +3 V.FIG. 29 shows C-Vg characteristics, likewise, resulting from scanningthe applied voltage Vg from +1 V to −1 V and thereafter scanning theapplied voltage Vg again to +1 V.

[0240] From FIG. 28, it can be understood that a write is done on thememory-functional film when the applied voltage Vg comes to −3 V, and ahysteresis characteristic appears with the graph shifted rightward.Although not shown, when the applied voltage Vg comes to +3 V, the curverecovers, making it understood that an erase is done. It is noted that astate of increased threshold is assumed as a write in this case. On theother hand, from FIG. 29, no hysteresis characteristic appears within arange of +1 V of applied voltage Vg, making it understood that neitherwrite nor erase is done. As shown above, from FIGS. 28 and 29, it can beunderstood that according to the characteristics of thememory-functional film in this embodiment, it is implementable toperform write and erase at ±3 V as well as nondestructive read that doesnot cause destruction of electric charges (i.e., storage) accumulated inthe memory-functional film at 1 V. Accordingly, as in the sixthembodiment in which the memory-functional film is implemented byconductor film, there is no need for applying such a high voltage as 14V or 18 V to between the control gate 115 and the P-type shallow wellregion 112, so that low voltage operation becomes implementable.

[0241] Next, the fabrication procedure of the semiconductor storagedevice of this embodiment is explained. The fabrication procedure of thesemiconductor storage device of this embodiment differs from thefabrication procedure of the foregoing sixth embodiment only in thefabrication procedure of the floating gate. The memory-functional filmformed of a composite member of the polysilicon film 117 and thediscrete dots 118, 119 can be formed, for example, by the followingprocedure.

[0242] That is, device isolation regions 113, N-type deep well region111 and P-type shallow well region 112 are formed in the same manner asin the fabrication procedure of the sixth embodiment. Thereafter, on theP-type shallow well region 112, 2nm silicon oxide film is formed in a900° C. N₂O atmosphere. Next, polysilicon is grown by LPCVD process in a620° C. SiH₄ atmosphere. By doing so, the polysilicon is grown into alayer form, by which 5 nm thick polysilicon film 117 is formed. Next,the surface of the polysilicon film 117 is oxidized by a thickness of 2nm in a 900° C. N₂O atmosphere. Then, silicon is grown by LPCVD processin a 620° C. SiH₄ atmosphere, silicon is not grown into a layered formbut formed into a dot form. In more detail, whereas polysilicon filmwould be grown into a layered form on an oxide film formed by thermallyoxidizing a silicon single crystal substrate, silicon is formed into adot form on an oxide film formed by thermally oxidizing polysilicon filmeven with the use of the same silicon growth conditions. Thus,first-layer silicon fine particles 118 are formed.

[0243] Next, by oxidation in a 900° C. N₂O atmosphere, the first-layersilicon fine particles 118 are oxidized at their surfaces but havecrystal silicon remaining in their interiors with diameters of about 5nm. Then, silicon is grown by LPCVD process in a 620° C. SiH₄atmosphere, by which the silicon is formed into a dot form, thussecond-layer silicon fine particles 119 being formed. These second-layersilicon fine particles 119 are in large part formed in adjacency to thefirst-layer silicon fine particles 118. That is, the second-layersilicon fine particles 119 are in large part formed obliquely upward ofthe first-layer silicon fine particles 118. Next, by oxidation in a 900°C. N₂O atmosphere, the second-layer silicon fine particles 119 areoxidized at their surfaces but have crystal silicon remaining in theirinteriors with diameters of about 5 nm. After the memory-functional filmis completed in this way, polysilicon film that serves as the controlgate 115 is formed by LPCVD process. It is noted that the number densityof silicon fine particles in a combination of the first-layer siliconfine particles 118 and the second-layer silicon fine particles 119 isabout 3×10¹¹ cm⁻².

[0244] According to the semiconductor storage device of this embodiment,as a result of forming the floating gate of a composite member of thepolysilicon film 117 and the discrete dots 118, 119, it is implementableto obtain a memory-functional film in which write is done at +3 V whilewrite is not done at ±1 V. Thus, it becomes implementable to performwrite and erase operations as well as nondestructive read at lowvoltage.

[0245] Furthermore, although the number of layers of discrete dotsconstituting the floating gate has been set to “2” in this embodiment,yet the present invention is not limited to this.

[0246] (Eleventh Embodiment)

[0247] This embodiment relates to a semiconductor-storage-device drivemethod by which the ratio of a voltage applied to the memory-functionalfilm of selected memory cells to a voltage applied to thememory-functional film of non-selected memory cells can be set to thelargest possible one in the semiconductor storage devices of the sixthto tenth embodiments.

[0248] Generally, in write or erase operation on memory cells, a largevoltage is applied to the memory-functional film of the selected memorycell. Then, some extent of voltage would inevitably be applied also tothe memory-functional film of non-selected memory cells. Therefore, forprevention of malfunction, it is preferable that the ratio of a voltageapplied to the memory-functional film of selected memory cells to amaximum value of voltages applied to the memory-functional film ofnon-selected memory cells is made as large as possible.

[0249] Generally, in a commonly practiced drive method, for example, foran erase operation, the voltage of a selected word line is set toV_(DD), and the voltage of a selected bit line is set to ground voltage,and the voltage of the other word lines and bit lines is set toV_(DD)/2. In this case, the voltage of V_(DD) is applied to thememory-functional film of selected memory cells, while the voltage of 0or V_(DD)/2 is applied to the memory-functional film of non-selectedmemory cells. Therefore, the ratio of the voltage applied to thememory-functional film of selected memory cells to the maximum value ofvoltages applied to the memory-functional film of non-selected memorycells is

[0250] In the drive method of the semiconductor storage device of thisembodiment, applied voltages to individual word lines W and bit lines Bfor write and erase operations are shown in Table 2.

[0251] Table 2:

[0252] Write: Bit line B (Non-Selected) Word line W (Selected) 0 −(1 −A) × V (Selected) Voltage applied to Voltage applied to −V film: film:−V −A × V (Non-Selected) Voltage applied to Voltage applied to −A × Vfilm: film: −A × V (1 − 2A) × V

[0253] Erase: Bit lineB (Selected) (Non-Selected) Word lineW −V −A × V(Selected) 0 Voltage applied to Voltage applied to film: V film: A × V(Non-Selected) Voltage applied to Voltage applied to −(1 − A) × V film:film: A × V −(1 − 2A) × V

[0254] Also, applied voltages to individual word lines W and bit lines Bfor write and erase operations with V=3V and A=1/3 in Table 2 are shownin Table 3.

[0255] Table 3:

[0256] Write: Bit line B (Selected) (Non-Selected) Word line W 0 (V) −2(V) (Selected) Voltage applied to Voltage applied to −3 (V) film: film:−3 (V) −1 (V) (Non-Selected) Voltage applied to Voltage applied to −1(V) film: film: −1 (V)  1 (V)

[0257] Erase: Bit line B (Selected) (Non-Selected) Word line W −3 (V) −1(V) (Selected) Voltage applied to Voltage applied to 0 (V) film: film: 3(V)  1 (V) (Non-Selected) Voltage applied to Voltage applied to 2 (V)film: film: 1 (V) −1 (V)

[0258] In Tables 2 and 3, since it is desirable that the voltage of theplate electrode Plt be constant, numerical values in a case where theplate electrode Plt are set to 0 V at all times are described, but thepresent invention is not limited to this case. Also, the bit lines B inTables 2 and 3 refer to the first bit line Ba and the second bit lineBw. Also, Tables 2 and 3 show a case where injection and ejection ofelectrons occurs from the channel side on the assumption that a state oflow threshold of the memory cell is a write state. In addition, voltagevalues of write operation and erase operation are reversed when theinjection and ejection of electrons occurs from the control gate (wordline W) side.

[0259] As shown in Table 2, in the drive method of the semiconductorstorage device of this embodiment, for a write operation, −V is appliedto the selected word line, −A×V is applied to non-selected word lines, 0is applied to the selected bit line, and −(1−A)×V is applied tonon-selected bit lines. Also, for an erase operation, a voltage of 0 isapplied to a selected word line, −(1−A)×V is applied to non-selectedword lines, −V is applied to a selected bit line, and −A×V is applied tonon-selected bit lines. In this case, it holds that 1/3≦A<1/2 (where acase with A=1/2 is equivalent to the case of the drive method that hashitherto been commonly practiced in terms of the voltages applied to thefilm).

[0260] As for the voltages for the above erase operation, the voltagesfor individual nodes (selected word line and non-selected word lines, aswell as selected bit line and non-selected bit lines) may be setuniformly higher within such a range that the voltage for thenon-selected bit lines does not exceed 0 (toward the positive side).However, if the voltage of the bit line B exceeds 0 V, there would flowa forward-junction leak current to the plate electrode Plt. The ratio ofthe voltage applied to the memory-functional film of a selected memorycell to the maximum value of voltages applied to the memory-functionalfilm of non-selected memory cells becomes a maximum of 3 (in absolutevalue) when A=1/3. Thus, the setting of A=1/3 is most preferable. Aspecific value for V in Table 2 may be determined optimally according tofilm quality or film structure. In more detail, it is preparatorily setthat injection or ejection of charges occurs when the absolute value ofthe voltage applied to the memory-functional film is V, while injectionor ejection of charges does not occur when the absolute value of thevoltage applied to the memory-functional film is A×V. In addition, for aread operation, the absolute value of the voltage applied to thememory-functional film is preferably set to not more than A×V, in whichcase there never occurs destruction of storage due to the readoperation.

[0261] Table 3 shows a specific example of Table 2 in a case where V=3Vand A=1/3. Whereas the absolute value of the voltage applied to thememory-functional film of the selected memory cell is 3 V, the absolutevalues of the voltages applied to the memory-functional film ofnon-selected memory cells are 1 V in all cases.

[0262] As described above, in the drive method of the semiconductorstorage device of this embodiment, the ratio of a voltage applied to thememory-functional film of a selected memory cell to a maximum value ofvoltages applied to the memory-functional film of non-selected memorycells can be made larger than conventional “2,” so that a memory havinglarge operational margin can be implemented.

[0263] In addition, in this embodiment, as can be seen from Table 2, itis necessary to apply different voltages to a selected bit line and anon-selected bit line. Therefore, this embodiment cannot be applied tothe fifth embodiment in which the well region is common to all thememory cells.

[0264] (Twelfth Embodiment)

[0265] This embodiment relates to a semiconductor storage device inwhich an SOI substrate is used to make up the semiconductor storagedevices of the foregoing fifth to eleventh embodiments. A plan view ofthe semiconductor storage device of this embodiment is the same as thatof FIG. 11 or FIG. 14.

[0266]FIG. 30 is a schematic sectional view of a memory cell in thesemiconductor storage device of this embodiment. When a body 124 betweenN⁺ diffusion layers 123 formed on an SOI layer 128 on buried oxide film122 stacked on a silicon substrate 121 is provided as a common body,then the semiconductor storage device operates in the same manner as inthe fifth embodiment. On the other hand, if arrays of the bodies 124isolated by the device isolation regions 125 are given independentvoltages, respectively, so as to be used as second bit lines, thenrandom access is enabled as in the sixth to tenth embodiments.

[0267] A memory-functional film 126 formed on the body 124 is adielectric film including a floating gate of conductive film or afloating gate composed of discrete dots. Otherwise, thememory-functional film 126 may also be given by the charge-trapping filmor the ferroelectric film having hysteresis characteristics. Referencenumeral 127 denotes a control gate. Further, although FIG. 30 shows acase of the completely depletion type, yet a partially depletion typemay also be adopted. In that case, the resistance of the body 124 thatbecomes the second bit line Bw can be reduced, allowing higher speed ofthe device to be implemented.

[0268] Next, the fabrication procedure of the semiconductor storagedevice of this embodiment is explained. First, dielectric deviceisolation regions 125 are formed in the body 124 formed on the SOIsubstrate 128. Subsequently, dopant injection into the body 124 isperformed so that the memory device has a proper threshold. Theformation of upper structure after this on is the same as in thesemiconductor storage devices of the fifth to tenth embodiments.

[0269] In the semiconductor storage device of this embodiment, thefollowing effects can be obtained in addition to the effects obtained bythe semiconductor storage devices and drive method of the fifth toeleventh embodiments. That is, in the semiconductor storage device ofthis embodiment, for the presence of the thick buried oxide film 122,the electrostatic capacity between the body 124 and the siliconsubstrate 121 can be made very small. In contrast, in the semiconductorstorage devices of the sixth to tenth embodiments, the electrostaticcapacity between the shallow well region 63, 82, 92, 102, 112 and thedeep well region 62, 81, 91, 101, 111 is quite large. Therefore,according to the semiconductor storage device of this embodiment, theconsumption current for charging the capacity with respect to the abovesubstrate can be made small, as compared with the semiconductor storagedevices of the sixth to tenth embodiments. From the above reasons, theuse of the SOI substrate makes it feasible to achieve power consumptionreduction.

[0270] (Thirteenth Embodiment)

[0271] An embodiment of the present invention is explained below withreference to FIG. 31. This embodiment relates to a semiconductor storagedevice in which a film having memory function is present on a side wallof the gate electrode. Further, 2-bit operation of such a device isexplained.

[0272] In a memory cell (FIG. 31) constituting the semiconductor storagedevice of this embodiment, an N-type first diffusion region 132 and anN-type second diffusion region 133 are formed on a surface of a P-typewell 131 formed in a semiconductor substrate, and a channel region isformed between these N-type diffusion regions 132, 133 and at anuppermost layer portion of the well 131. On this channel region isformed a gate electrode 135 via a gate insulator 134 formed of siliconoxide film or silicon nitride film having a film thickness of about 1 nmto 6 nm. The gate electrode 135 does not overlap with the diffusionregions 132, 133, where there is left a slight channel region (139 inFIG. 31) that is not covered with the gate electrode 135.

[0273] In this case, the gate electrode 135 is formed of part of a wordline structured in the same manner as the word line of the foregoingindividual embodiments.

[0274] At both ends of the gate electrode 135 is formed a gate side-wallinsulator. This gate side-wall insulator is made up of a charge-holdingfilm 136 and silicon oxide film 137. The charge-holding film 136 can begiven by, for example, silicon nitride film. In this semiconductorstorage device, it is portions of charge accumulating regions 138′, 138in the charge-holding film 136 that electric charges are actuallyaccumulated or trapped to hold storage.

[0275] Next, the principle of write operation in this semiconductorstorage device is explained. It is assumed here that write refers toinjecting electrons into the charge-holding film. In order to inject(write) electrons into the charge accumulating region 138 of thecharge-holding film 136, the first diffusion region 132 is assigned forthe source electrode, and the second diffusion region 133 is assignedfor the drain electrode. For instance, it is appropriate that 0 V isapplied to the first diffusion region 132 and the well 131, +6 V isapplied to the second diffusion region 133, and +2 V is applied to thegate electrode 135. According to such voltage conditions, an inversionlayer extends from the first diffusion region 132 (source electrode),but does not reach the second diffusion region 133 (drain electrode),causing occurrence of a pinch-off point. Electrons are accelerated by ahigh electric field from the pinch-off point to the second diffusionregion 133 (drain electrode), resulting in so-called hot electrons.These hot electrons are injected into the charge accumulating region138, by which write is done. It is noted that in the neighborhood of thecharge accumulating region 138′, hot electrons are not generated andtherefore write is not done.

[0276] As shown above, write can be accomplished by injecting electronsinto the charge accumulating region 138.

[0277] On the other hand, in order to inject (write) electrons into thecharge accumulating region 138′, the second diffusion region 133 isassigned for the source electrode, and the first diffusion region 132 isassigned for the drain electrode. For instance, it is appropriate that 0V is applied to the second diffusion region 133 and the well 131, +6 Vis applied to the first diffusion region 132, and +2 V is applied to thegate electrode 135. Like this, in a case of injecting electrons into thecharge accumulating region 138, the source region and the drain regioncan be replaced with each other so that electrons can be injected intothe charge accumulating region 138′, by which write can be done.

[0278] Next, the principle of read operation in this semiconductorstorage device is explained. In order to read information stored in thecharge accumulating region 138′, the first diffusion region 132 isassigned for the source electrode, while the second diffusion region 133is assigned for the drain electrode, and the transistor is put into asaturation region operation. For instance, it is appropriate that 0 V isapplied to the first diffusion region 132 and the well 131, +2 V isapplied to the second diffusion region 133, and +1 V is applied to thegate electrode 135. In that case, if electrons have not been accumulatedin the charge accumulating region 138′, the drain current easily flows.If electrons have been accumulated in the charge accumulating region138′, on the other hand, the inversion layer is less easily formed inthe neighborhood of the charge accumulating region 138′, so that thedrain current less easily flows. Therefore, stored information of thecharge accumulating region 138′ can be read by detecting the draincurrent. In this operation, the presence or absence of accumulatedcharges in the charge accumulating region 138 does not affect the draincurrent because the neighborhood of the drain is pinched off.

[0279] Also, for reading the information stored in the chargeaccumulating region 138, the second diffusion region 133 is assigned forthe source electrode, the first diffusion region 132 is assigned for thedrain electrode, and the transistor is put into a saturation regionoperation. For instance, it is appropriate that 0 V is applied to thesecond diffusion region 133 and the well 131, +2 V is applied to thefirst diffusion region 132, and +1 V is applied to the gate electrode135. Like this, information stored in the charge accumulating region 138can be read by replacing the source region and the drain region witheach other in reversal to the case of reading information stored in thecharge accumulating region 138′.

[0280] Furthermore, in the case where there is left a channel region 139that is not covered with the gate electrode 135, an inversion layer isdissipated or formed in the channel region that is not covered with thegate electrode 135 depending on the presence or absence of excesselectrons of the charge accumulating regions 138′, 138, so that a largehysteresis (threshold change) is obtained. However, if the channelregion 139 that is not covered with the gate electrode 135 is too largein width, the drain current would decrease to a large extent, resultingin a large reduction in read speed. Therefore, preferably, the width ofthe channel region 139 that is not covered with the gate electrode 135is determined so that sufficient hysteresis and read speed can beobtained.

[0281] In the case where the diffusion regions 132, 133 extent to reachan end of the gate electrode 135, that is, where the diffusion regions132, 133 and the gate electrode 135 overlap each other, the thresholdvalue of the transistor is hardly changed by the write operation, butthe parasitic resistance at source end and drain end is largely changed,so that the drain current largely decreases (to one order or more).Therefore, read operation can be done by detecting the drain current,thus allowing a memory function to be obtained. However, when evenlarger memory hysteresis effect is needed, it is preferable that thediffusion regions 132, 133 and the gate electrode 135 do not overlapeach other.

[0282] Further, the principle of read operation in this semiconductorstorage device is explained.

[0283] First, as a first method, for erasing information stored in thecharge accumulating region 138′, it is appropriate that a positivevoltage (e.g., +6 V) is applied to the first diffusion region 132, 0 Vis applied to the well 131, a reverse bias is applied to the PN junctionbetween the first diffusion region 132 and the well 131, and moreover anegative voltage (e.g., −5 V) is applied to the gate electrode 135. Inthis case, in the PN junction in the neighborhood of the gate insulator,in particular, the potential gradient becomes steeper due to an effectof the gate electrode 135 to which the negative voltage is applied. As aresult, hot holes are generated on the well region 131 side of the PNjunction by interband tunneling. These hot holes are pulled in towardthe gate electrode 135 having a negative voltage, so that hole injectioninto the charge accumulating region 138′ is performed. In this way,erase operation of the charge accumulating region 138′ is carried out.In this case, 0 V may appropriately be applied to the second diffusionregion 133.

[0284] Also, for erasing information stored in the charge accumulatingregion 138, the voltages of the first diffusion region 132 and thesecond diffusion region 133 may be replaced with each other in theabove-described case of erasing information stored in the chargeaccumulating region 138′.

[0285] As a second method, for erasing information stored in the chargeaccumulating region 138′, it is appropriate that a positive voltage(e.g., +5 V) is applied to the first diffusion region 132, 0 V isapplied to the second diffusion region 133, a negative voltage (e.g., −4V) is applied to the gate electrode 135, and a positive voltage (e.g.,0.8 V) is applied to the well 131. In this case, a forward voltage isapplied to between the well 131 and the second diffusion region 133, sothat electrons are injected into the well 131. The injected electronsare diffused up to the PN junction between the well 131 and the firstdiffusion region 132, where the electrons are accelerated by an intenseelectric field, resulting in hot electrons. These hot electrons makeelectron-hole pairs generated in the PN junction. Part of the electronsand holes generated in this way, to which further energy is imparted bythe electric field, makes new electron-hole pairs generated. Thus, evenmore electron-hole pairs are generated in the PN junction between thewell 131 and the first diffusion region 132. That is, by applying aforward voltage to between the well 131 and the second diffusion region133, electrons injected into the well 131 act as a trigger for the yieldof the PN junction placed on the opposite side. Then, the hot holesgenerated in the PN junction are pulled in toward the gate electrode 135having a negative voltage, by which hole injection into the chargeaccumulating region 138′ is done.

[0286] According to this second method, in the PN junction between thewell 131 and the first diffusion region 132, even with the applicationof only a voltage that is insufficient to make hot holes generated byinterband tunneling, electrons injected from the second diffusion region133 act as a trigger for the yield of the PN junction, so that hot holescan be generated. Thus, the voltage for erase operation can be lowered.

[0287] Furthermore, for erasing information stored in the chargeaccumulating region 138′, whereas +6 V has to be applied to the firstdiffusion region 132 in the first erase method, +5 V suffices in thesecond erase method. Thus, according to the second method, the voltagefor erase operation can be reduced. Therefore, power consumption can bereduced, and deteriorations of the semiconductor storage device due tohot carriers can be suppressed.

[0288] By the above-described operational method, write and eraseoperations of selective two bits per transistor become implementable.

[0289] According to the semiconductor storage device of this embodiment,since a film having memory function is present on the side wall of thegate electrode 135, the gate insulator 134 itself does not need to havethe memory effect. Therefore, the gate insulator 134 can be easilyformed into a thinner film, so that the short-channel effect can beeasily suppressed. Further, the film having memory function is separatedeffectively by the gate electrode 135, so that 2-bit operation can beeasily implemented. Therefore, micro-finer implementation and costreduction of the semiconductor storage device can be easily achieved.

[0290] In addition, in this embodiment, the memory cell is formed on theP-type well 131 formed in a semiconductor substrate. Otherwise, thememory cell may be formed on a semiconductor substrate.

[0291] Furthermore, the present invention is not limited to the aboveindividual embodiments, and those embodiments may be combined withoutproblems. For instance, the first bit lines 12 in the first embodiment(FIGS. 1 to 4) and the second embodiment (FIG. 6) may well be replacedwith plates similar to the plates 48, 70 in the fifth embodiment (FIGS.11 to 16) and the sixth embodiment (FIGS. 18 to 21). Also, the plates48, 70 in the fifth embodiment (FIGS. 11 to 16) and the sixth embodiment(FIGS. 18 to 21) may well be replaced with bit lines similar to thefirst bit lines 12 in the first embodiment (FIGS. 1 to 4) and the secondembodiment (FIG. 6).

1. A semiconductor storage device characterized in that: on a topsurface of a semiconductor substrate (17, 41), device isolation regions(16) each extending and meandering in one direction are formed so as tobe arrayed with respect to a direction vertical to the one direction,and active regions each extending in the one direction are definedbetween neighboring ones of the device isolation regions (16),respectively; dopant diffusion regions (19) each serving as a sourceregion or drain region are formed at individual turnover portions,respectively, of meanders within the active regions, and channel regionsare defined between neighboring ones of the dopant diffusion regions(19) within identical active regions, respectively; on the semiconductorsubstrate (17, 41), word lines (11, 45) extending in intersection withthe one direction are provided so as to run on the channel regionsprovided within the active regions; and on the semiconductor substrate(17, 41), a plurality of bit lines (12, 13, 51) extending in the onedirection are provided so as to run on the dopant diffusion regions(19), and are also connected to the dopant diffusion regions (19)present thereunder via contact holes, respectively.
 2. The semiconductorstorage device according to claim 1, wherein the plurality of bit lines(12, 13) comprise a first bit line (12) provided so as to run on thedopant diffusion region (19) provided at a one-side turnover portion ofthe meander within an identical active region, and a second bit line(13) provided so as to run on the dopant diffusion region (19) providedat the other-side turnover portion of the meander within the identicalactive region.
 3. The semiconductor storage device according to claim 2,wherein the first bit line (12) and the second bit line (13) are formedof different interconnect layers electrically isolated by an interlayerinsulator (20), respectively.
 4. The semiconductor storage deviceaccording to claim 1, wherein the plurality of bit lines (51) arealternately connected to the dopant diffusion regions present thereundervia contact holes, respectively; and plate electrodes (48) are connectedto dopant diffusion regions to which the plurality of bit lines (51) arenot connected.
 5. The semiconductor storage device according to any oneof claims 1 to 4, wherein a film (21, 46) having memory function ispresent between gate electrode forming part of the word line (11, 45)and channel region.
 6. The semiconductor storage device according to anyone of claims 1 to 4, wherein a film having memory function is presenton a side wall of the gate electrode forming part of the word line.
 7. Asemiconductor storage device characterized in that: on a top surface ofa semiconductor substrate (61), device isolation regions (64) eachextending in one direction are formed so as to be arrayed with respectto a direction vertical to the one direction, and active regions eachextending in the one direction are defined between neighboring ones ofthe device isolation regions (64), respectively; dopant diffusionregions (66) each serving as a source region or drain region are formedwithin the active regions, and channel regions are defined betweenneighboring ones of the dopant diffusion regions (66) within identicalactive regions, respectively; on the semiconductor substrate (61), aplurality of word lines (67) extending in intersection with the onedirection are provided so as to run on the channel regions providedwithin the active regions; on the semiconductor substrate (61), aplurality of bit lines (65) extending in the one direction are providedso as to run on the dopant diffusion regions (66), and are alsoconnected to the dopant diffusion regions (66) present thereunder viacontact holes, respectively; and the semiconductor substrate (61) has awell region (63) on its top surface side, the well region (63) beingelectrically partitioned by the device isolation regions (64) to formthird bit lines.
 8. The semiconductor storage device according to claim7, wherein the plurality of bit lines comprise a first bit lineconnected to one of the source region or the drain region, and a secondbit line connected to the other one of the source region or the drainregion.
 9. A semiconductor storage device characterized in that: on atop surface of a semiconductor substrate (17), device isolation regions(16) each extending and meandering in one direction are formed so as tobe arrayed with respect to a direction vertical to the one direction,and active regions each extending in the one direction are definedbetween neighboring ones of the device isolation regions (16),respectively; dopant diffusion regions (19) each serving as a sourceregion or drain region are formed at individual turnover portions,respectively, of meanders within the active regions, and channel regionsare defined between neighboring ones of the dopant diffusion regions(19) within identical active regions, respectively; on the semiconductorsubstrate (17), a plurality of word lines (11) extending in intersectionwith the one direction are provided so as to run on the channel regionsprovided within the active regions; on the semiconductor substrate (17),a plurality of bit lines (12, 13) extending in the one direction areprovided so as to run on the dopant diffusion regions (19), and are alsoconnected to the dopant diffusion regions (19) present thereunder viacontact holes, respectively; and the semiconductor substrate (17) has awell region (26) on its top surface side, the well region (26) beingelectrically partitioned by the device isolation regions (16) to formthird bit lines.
 10. The semiconductor storage device according to claim9, wherein the plurality of bit lines (12, 13) comprise a first bit line(12) provided so as to run on the dopant diffusion region (19) providedat a one-side turnover portion of the meander within an identical activeregion, and a second bit line (13) provided so as to run on the dopantdiffusion region (19) provided at the other-side turnover portion of themeander within the identical active region.
 11. The semiconductorstorage device according to claim 8 or 10, wherein the first bit line(12) and the second bit line (13) are formed of different interconnectlayers electrically isolated by an interlayer insulator (20),respectively.
 12. The semiconductor storage device according to claim 7or 9, wherein the plurality of bit lines (65) are alternately connectedto the dopant diffusion regions present thereunder via contact holes,respectively; and plate electrodes (70) are connected to dopantdiffusion regions (66) to which the plurality of bit lines (65) are notconnected.
 13. The semiconductor storage device according to any one ofclaims 7 to 12, wherein a film (21, 68) having memory function ispresent between gate electrode forming part of the word line (11, 67)and channel region.
 14. The semiconductor storage device according toany one of claims 7 to 12, wherein a film (138 138′) having memoryfunction is present on a side wall of the gate electrode (135) formingpart of the word line.
 15. The semiconductor storage device according toany one of claims 5, 6, 13 and 14, wherein the film having memoryfunction is a dielectric film (33, 87, 98, 116) containing fineparticles (32, 86, 96, 97, 118, 119) formed of a semiconductor orconductor in a dot form.
 16. The semiconductor storage device accordingto any one of claims 5, 6, 13 and 14, wherein the film having memoryfunction is a multilayered film of a silicon nitride film and a siliconoxide film.
 17. The semiconductor storage device according to any one ofclaims 5, 6, 13 and 14, wherein the film having memory function is sostructured that a silicon nitride film is sandwiched by silicon oxidefilms.
 18. The semiconductor storage device according to any one ofclaims 5, 6, 13 and 14, wherein the film having memory function is sostructured that a silicon film (117) is sandwiched by silicon oxidefilms (116).
 19. The semiconductor storage device according to claim 18,wherein the silicon film is formed of polysilicon (117).
 20. Thesemiconductor storage device according to any one of claims 1 to 19,wherein part of the word line (11, 45, 67) present on the channel regionforms a gate electrode.
 21. The semiconductor storage device accordingto any one of claims 1 to 20, wherein in a write operation or an eraseoperation, in a selected memory cell, if an absolute value V of apotential difference between the word line (45, 67) and the bit line(51, 65), or an absolute value V of a potential difference between theword line (11) and the first bit line (12), or an absolute value V of apotential difference between the word line (11) and the second bit line(13), or an absolute value V of a potential difference between the wordline (11, 67) and the third bit line (26, 63), is V=V_(DD), then arelationship that V_(DD)/3≦V<V_(DD)/2 is satisfied with respect to amemory cell connected to only either one of a selected word line and aselected bit line.
 22. A semiconductor integrated circuit in which thesemiconductor storage device as defined in any one of claims 1 to 21 anda logic circuit are compositely mounted.